From: Brown, RM (Bob) - PPD [R.M.Brown@rl.ac.uk]
Sent: 15 December 2004 16:20
To: Mark Raymond; claire.shepherd-themistocleous@rl.ac.uk; Lodge, AB
(Tony); Bell, Ken; matthew.ryan@imperial.ac.uk
Cc: Cockerill, DJA (David)
Subject: RE: protection resistor noise

Mark, thanks for this.
  
My current thinking is to reduce the dynamic range by decreasing C(f) to 6.8pF, giving full scale = 10.5 pC.
This is because the crystal and VPT will 'age' reducing the charge/MeV with time.  At the start we can reduce the VPT bias to avoid saturation, then increase the bias later to compensate for aging.

However, I now realise that although decreasing the MGPA full scale decreases the R(f) noise, this improvement is offset by an increase in the FET noise, which starts to become important when C(f) becomes small.

Have I understood correctly?  What is your estimate for the total noise with C(f) = 6.8 pF and R(f) = 5.6k?

Bob. 

-----Original Message-----
From: Mark Raymond [mailto:m.raymond@imperial.ac.uk]
Sent: 15 December 2004 13:20
To: claire.shepherd-themistocleous@rl.ac.uk; Lodge, AB (Tony); Bell, Ken; matthew.ryan@imperial.ac.uk; Brown, RM (Bob) - PPD
Subject: protection resistor noise


Hi,

I gave some consideration to the noise contribution of a possible 
protection resistor and am attaching a note. I was too pessimistic about

its noise contribution as you can see, but it depends on where you put
it. 
If it can go on the HV card, close to the VPT then its contribution will
be 
small. If it goes on the motherboard and sees the significant
capacitance 
of the umbilical cable, then its contribution will be much larger.

I assume this accounts for Claire's measurements.

Cheers, Mark.

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  Mark Raymond
  Blackett Laboratory
  Imperial College       phone: +20 7594 7799
  London SW7 2AZ         fax: +20 7823 8830
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