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BCID Demonstrator

BCID/FADC card tests with the Phase I demonstrator

In June and September 1995, we again carried out test beam runs to prove under realistic conditions various bunch crossing identification algorithms implemented in Xilinx field programmable gate arrays and in an ASIC (designed by the University of Heidelberg), and high speed flash analogue to digital converter cards also designed by IHEP in Heidelberg. We also used a new data acquisition suite running under LynxOs instead of OS9.

This is the specification for the programming model, and the diagnostics programs that were written to help test and debug the BCID cards. There is also a document describing the June 1995 event format and the September 1995 event format.

Comments and requests for clarification may be sent to Norman.Gee@rl.ac.uk

12 November 1995

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