ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 04 May 1999

Minutes

Present: Tony Gillman, Bob Hatley, Viraj Perera, Richard Staley

1. ACTION list from previous meeting (20-4-1999):
a) Richard has almost completed the write-up of the backplane transmission tests, which 
may be produced as an ATLAS note. (He has also succeeded in getting the GTL system 
to work at 160 Mbit/s (previously limited to 80 Mbit/s, with poor eye-patterns), by 
running the devices at 3.0 V and terminating the driven lines with 25 ohms instead of 50 
ohms.)
b) Some progress has been made towards resolving the outstanding issues relating to the 
ROD prototype specifications, and further discussions between Norman, Tony and Viraj 
will be arranged.
c) The proposed workplan for the CCM prototype programme is still awaited from Tony 
and Viraj.

2. DSS system:
a) DSS motherboard design/layout status
Viraj reported that the schematics were finally completed and sent to the Drawing 
Office on 28th April 1999. In Darren's absence, Kevin has started component 
placement. He has found that the current FPGA package sizes will not permit the S-link 
connector to be mounted on the same side of the board, so it will be mounted on the 
other face, thereby adding one extra width unit to the module. (Of course, for non-S-link 
uses this connector need not be mounted.) It may also be possible at a much later stage 
to re-layout the board to allow the S-link connector to be mounted alongside smaller 
FPGAs, if considered useful.
Bob pointed out that we must not overlook the potential cooling problems with closely-
packed, dense double-sided boards in this system.
Tony requested Viraj to obtain a breakdown of the projected layout time for this board 
from Chris Day.
ACTION: Obtain breakdown of mother-board layout time from Drawing Office - Viraj
b) LVDS daughter-cards status
Richard reported that both these cards had been sent for manufacture during the 
previous week (w/b 26th April 1999). Five pcbs will be made, four of which will be 
assembled. All components are available or on order, with only the Berg 2mm 
connectors on long delivery (as already noted). While waiting for manufacture and 
assembly he will prepare a simple test jig to allow basic card functions (power, clocks, 
etc.) to be tested before the DSS motherboards are available for full testing.
c) G-link daughter-cards status
Bob reported that the Rx card was sent for manufacture also during the w/b 26th April 
1999. Four pcbs will be made, two of which will be assembled. Bob has arranged for 
eight 2m SMR cable assemblies to be manufactured. It was decided that adapting 
Richard's simple test jig for basic tests would prove too difficult.
For the Tx card, component placement is almost complete but no tracking has yet been 
started. As Darren will now switch to the high-priority DSS motherboard layout, further 
progress must await its completion.

3. ASIC designs:
a) Serialising ASIC or Serialising FPGA?
Viraj had no further information from Ian on his ongoing simulation studies with the 
Xilinx VIRTEX FPGAs. As reported at last week's Group Meeting, he currently appears 
to hit a speed limit of ~131 MHz, but expects this to increase significantly with further 
optimisation. The crucial question is whether the speed can reach (and exceed by a 
comfortable margin) 160 MHz.
In addition, it was noted that further work is needed to implement all the functions 
resulting from the BC-demux scheme.
b) CP ASIC status and schedule
There was some discussion about how much work was needed to complete a first draft 
of the specifications for this device. Viraj has already written some parts of the 
document (including all the chapter headings), and it was felt that other people could 
usefully contribute, in particular to the sections detailing the algorithms. Physicist effort 
to define the algorithms in pseudo-code would be especially valuable in this area.
It was again remarked that a C-to-VHDL translator could prove to be a very important 
tool for the actual design process.
ACTION: Produce an estimate of the likely timescale for completing the design 
specifications - Viraj

4. CCM prototype:
a) Review plans
Tony proposed that Draft 4.0 of the design specifications should now be put up on the 
Web and the reviewers invited to begin assessing it. They should aim to spend the next 
two weeks or so going through it in detail, with a view to completing (?) the review 
process by early-June.

5. CPM prototype:
a) Update
Richard will dust off the draft document that he wrote many weeks ago and get it into a 
form which we can start discussing informally.
ACTION: Prepare Draft 0 of the CPM prototype specifications document - Richard

6. Any other business:
Tony mentioned that he had responded to a recent request from CERN for an estimate 
of our total pcb requirements. Apparently there is a potential safety issue regarding 
materials containing bromine, which involves normal printed circuit boards. All 
subsystems are invited to estimate their expected "hectareage" of such materials - ours 
would appear to be around 70 m2.

* Next meeting - Tuesday 11th May at 11.00 - CR01, R1 at RAL.

Tony Gillman