ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 9 February 1999

Minutes:

Present:	Eric Eisenhandler, John Garvey, Norman Gee, Tony Gillman,
Bob 			Hatley, Viraj Perera, Richard Staley

1. ACTION list from previous meeting (2-2-1999):
a) Richard has been successfully accessing the RAL CADENCE system from
Birmingham, but currently only via the Drawing Office machine. As all
external users will soon only be able to access one specific machine,
proper authorisation must be set up for him.
b) Norman, Sam and Uli have been exchanging e-mails regarding the pin
numerology of the Jet/Energy Sum trigger backplane. To discuss this further
a meeting with a small number of people will be arranged at some convenient
time/place before the Birmingham Joint Meeting.
c) John reported that Bill Stokes (Birmingham) is now working with Scott to
prepare a test plan for the DSS/LVDS system, using the old TXM test plan as
a guide.
d) Richard has been in contact with GORE regarding twin-ax cable
assemblies. There is a lead-time of 4-6 weeks for custom orders. The AMP
connectors are also on a 4-6 week delivery. FCI, a possible alternative
manufacturer of both, has been contacted and Richard is awaiting a reply
from them. Conformance of any of theses cables with the CERN safety
requirements is as yet unclear and will be pursued.
e) Tony reported that the RAL Drawing Office have confirmed the proposed
timescales for the various board designs in general, but the LVDS tests
could be made three weeks earlier if Kevin Hatton carried out the DSS
motherboard layout.
f) Read CCM prototype draft and feed comments to Viraj - no comments yet
received.
g) Read CPM prototype draft and feed comments to Richard - no comments yet
received.
h) Tony reported that all the people for the next three review panels - for
the Serialising ASIC, CCM prototype and CP ASIC - have now been contacted
with proposed dates.
i) Norman has sent the TXM test plan for Scott and Bill Stokes to
Birmingham (see item 1c above).

ACTION: Clarify situation regarding appropriate authorisation for external
use of RAL CADENCE system - Richard
ACTION: Continue dialogue with Sam and Uli on Jet/Energy Sum processor
backplane issues, and arrange technical meeting - Norman
ACTION: Prepare test plan for the DSS system - Norman/Scott/Bill
ACTION: Discuss CERN safety requirements for cables with Uli (et al.) - Tony
ACTION: Agree who should do DSS motherboard layout - Viraj
ACTION: Read CCM prototype draft and feed comments to Richard - ALL

2. CMOS/GTL backplane test cards - status and timescale:
Richard now has two assembled cards which he and Scott will start testing
in Birmingham this week. The aim is to complete these tests by the end of
February, so that the Serialising ASIC and CP ASIC I/Os can be finally
specified.
Norman proposed that the results and conclusions of all such lab tests be
written up and made public - where appropriate as ATLAS notes.
ACTION: Complete and document backplane driver tests by 28/2 - Richard/Scott

3. DSS system:
a) Motherboard design status:
Viraj reported that James is working on the FPGA coding and targeting
suitable devices, Azmat on the VME interfacing and Kevin is creating the
necessary CADENCE library components. He will then move on to schematic
capture for the full board. The dual-port RAMs, with a 4-6 week delivery
time, are now being ordered.
b) LVDS daughter-card design status:
Richard has started schematic capture and component creation using the RAL
CADENCE system. Feedback on the specifications will happen during the
review, which he would like as soon as possible.
c) G-link daughter-card design status:
Bob reported that the Tx schematic design is almost complete, and the Rx
design is starting now. The serial connector type still needs to be
specified.
d) Serial link connectors/cables - which type?:
A discussion (after the meeting) concluded with the following points:
Three series of test are planned for the DSS/LVDS system -
	i) "loop-back" tests to verify electronics with short (e.g. 2m) cables
	ii) "scan" tests across a range of cable lengths - 10m, 12m, 14m,
16m, 18m, 20m
	iii) system-wide tests with "safe" cable length across all 32 channels
The tests would ideally be done in this order, but because of the long
lead-times to obtain customised cable assemblies we may need to "estimate"
a safe length in advance. The suggested "safe" figure was 12m. Do GORE
supply standard length assemblies off-the-shelf? How much of the total
cable assembly cost is material, and what does it cost? Could we afford to
buy the assembly tooling (if any)? Richard will try to get answers to these
and other questions.
Regarding connectors, it was decided for the LVDS daughter-cards to use the
FCI 2mm-grid male board-mounting blocks, which would enable a final CPM to
contain all I/O on the backplane connector.
The G-link daughter-cards will serve two purposes - primarily to test the
DSS-ROD links but secondarily to test the PPr-Trigger Processors fall-back
solution of G-link if LVDS proves unsatisfactory. It was therefore decided
to provide both a METRAL 4mm-pitch mini-coaxial connector block (for the
DSS-ROD case) and an FCI 2mm-grid male connector (for the PPr-Trigger
Processors case), with 50-ohm transmission line PCB traces to each,
selected by short solder-bridge links. This would enable the G-links to be
run in either differential or single-ended mode. (Note that 4mm METRAL
connectors would still allow the PPr inputs to use the CPM backplane
connector if the G-links were to be run in single-ended mode - if
differential the front-panel would need to be used.)
e) Review status:
Tony reported that some comments on the DSS/LVDS/G-link system had been
received from a small number of people so far. The cut-off date was ~Monday
15th February.
f) Daughter-card components - library parts creation and ordering:
Bob offered to act as the interface with the Drawing Office for parts
creation for all designs. In addition, he will compile a list of long
lead-time parts common to all designs and organise ordering.

ACTION: Obtain more information from GORE - Richard
ACTION: Compile list of (common) long lead-time components - Bob

4. ROD prototype design status:
Viraj reported that schematic capture for this module is currently awaiting
Kevin's return from DSS work, which is more urgent.

5. Serialising ASIC specifications and design status:
The specifications are almost complete, and will be available for posting
to the Web by ~12th February. Ian Brawn is still working on the VHDL model.

6. CCM prototype design schematics:
Viraj reported on a few details of the design that Kevin is still looking into.

7. CPM prototype - proposed amended timescale:
Tony noted that the timescale for this module was unnecessarily aggressive
- as it will require tested CP ASICs, which will not be available until
mid-2000, the PDR and design can clearly be delayed by several months. This
will significantly ease the current very high workload.

ACTION: Produce a new design/manufacturing schedule to reflect this change
- Tony

8. Any other business:
There was none.

* Next meeting - Tuesday 16th February at 11.00 in CR1, RAL.

Tony Gillman