ATLAS Level-1 Calorimeter Trigger Hardware Progress Meeting - 09 March 1999 Minutes: Present: Eric Eisenhandler, John Garvey, Tony Gillman, Bob Hatley, Viraj Perera, Richard Staley 1. ACTION list from previous meeting (02-3-1999): a) Norman and Viraj had discussed the JEP backplane with Uli and Magnus during the Birmingham meeting and some progress was made towards a viable Common Merger Module, but more study is needed. b) CCM draft specifications awaiting comments from all c) New CPM prototype schedule needed from Tony d) Bob has received a reply from Raychem regarding suitable link cables, but the cost is unacceptable. He will continue to investigate. e) Richard presented some nice preliminary results at the Birmingham meeting from the backplane CMOS Test Card. He will next transmit CMOS and GTL data between a pair of cards via the JEM-2 backplane segment. The results will be documented by 19th March at the latest. f) Norman has prepared a draft 0 exploitation plan for the link tests, which was discussed at the Birmingham Software meeting. g) Tony will contact the appropriate people at CERN regarding loaning water-cooled racks. h) Viraj has produced an interim DSS programming model for the software group. i) Richard submitted the DSS LVDS daughter-card design to the Drawing Office last week for layout. j) Bob submitted the DSS G-link daughter-card design to the Drawing Office last week for layout, but if necessary it will be queued behind the LVDS card, which has the higher priority. k) Initial tests of the DSS and ROD prototype modules would use the old demonstrator TCM, which is able to provide suitable clock and start/stop signals. A simple interface card will be designed by Kevin to accept these signals (preferably in NIM/Lemo 00 format). ACTION: Continue discussions with Uli/Sam/Magnus on Common Merger Module and associated backplane issues - Norman/Tony ACTION: Read and comment on CCM draft specifications - ALL ACTION: Produce draft schedule for CPM prototype - Tony ACTION: Produce new CPM prototype schedule - Tony ACTION: Produce a summary of cable options for link tests - Bob ACTION: Complete backplane transmission tests and document - Richard/Scott ACTION: Contact CERN regarding loan of water-cooled racks to RAL - Tony ACTION: Complete final DSS specifications documents and post to Web - Viraj/Bob/Richard 2. CMOS/GTL backplane cards: Richard described his latest thoughts on how the CPM prototype backplane signals might be partitioned and grouped. 3. DSS system: a) Motherboard design status - Viraj reported that Azmat is currently targeting programmable devices to handle the VME protocol logic. James has had some problems with the FPGA timing simulations, and some re-design has been needed. Kevin should complete the schematics and pass the files to the Drawing Office by 22nd March. They estimate the layout will take them 3 weeks. To ensure compatibility with the Heidelberg MCM Test module, Ulrich would like to see a copy of the schematics. b) LVDS link cable lengths - Tony suggested that BER measurements should be done driving one (or two) channels, with cable lengths ranging from 10m - 20m in 2m steps, to get an estimate of maximum safe cable length. A 32-channel system test with 10m cables (assumed geometrically comfortable in ATLAS?) will follow. c) Timescale for tests and link decision - Tony estimated that the LVDS daughter-cards would not be available before 23rd April, with the DSS motherboards arriving about a week later. This would imply LVDS system tests not starting until at least w/b 10th May, so a final decision on link technology could not be taken much before the end of May. ACTION: Send Ulrich the .ps file(s) of the DSS/G-link schematics - Viraj/Bob 4. ROD prototype: a) Design status - Viraj reported that the review exercise had exposed several areas where more thinking was needed - for example, in the area of event fragment formats. How closely does the prototype need to resemble the final design? About a week will be needed to update the specifications after these points have been resolved, and at least another month to complete the FPGA design and schematics before the board can go for layout. ACTION: Resolve remaining specification issues by the end of March - Norman/Viraj 5. CCM prototype: a) Design status - Viraj reported that Kevin will start to design an ECL Clock Control receiver module for the first stage of DSS system testing - to be followed by the second stage when the TTCrx module will be used. The CAN-bus work has been delayed by technical problems. 6. System test software status: Eric reported briefly on progress towards getting the necessary software prepared for the DSS and ROD prototype test programme. The work that Kithsiri is doing on the diagnostics panels for the new modules is progressing well. Norman will visit Birmingham to work with Scott and Bill, who have started to define the DAQ needs of the system following Norman's draft 0 exploitation plan. In the longer term, the aim is to obtain the ATLAS DAQ software from CERN. 7. Any other business: Eric reminded everyone of the forthcoming UK group meeting on Friday 19th March. It was agreed that this should be of a more restricted length than usual as we had only just emerged from a 2.5-day joint meeting at Birmingham! * Next meeting - Tuesday 16th March at 11.00 in CR13, RAL. Tony Gillman