ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 11 May 1999

Minutes

Present: John Garvey, Norman Gee, Tony Gillman, Viraj Perera, Richard Staley

1. ACTION list from previous meeting (04-5-1999):
a) As the write-up of the backplane transmission tests is now essentially
complete, Richard was encouraged to release it fairly soon as an ATLAS
note. It was felt to be more important to make the information available
quickly rather than have a very polished document.
b) Viraj, Norman and Tony have still not managed to get together to discuss
the remaining important issues regarding the ROD prototype specifications.
They agreed to meet on Monday 17th May at 10.00.
c) Viraj would prefer to wait another week before discussing a work-plan
for the CAN-bus part of the CCM prototype programme. He added that the
TTCvi module is now available from CERN (SF2500), and the 4-fibre version
of the TTCvx module suitable for our system will be available by mid-June
(SF900). It was decided to order one of each module now, with a further
pair later if needed for a second system.
d) (The discussion of the DSS mother-board layout time estimate is reported
below under item 2a)
e) (Discussion about the timescale for producing the CP ASIC specifications
document is reported below under item 3b)
f) Richard has put draft 0 of the CPM prototype specifications document on
the Web (www.ep.ph.bham.ac.uk/user/staley/)

2. DSS system:
a) DSS motherboard design/layout status
Viraj reported that the layout is going well, with all the large components
now placed. As board real-estate is very tight smaller packages are being
having to be found for some components, which is taking extra time. The
Drawing Office have estimated the time to complete the layout as follows:
3-5 days for placement of the remaining small components
3 days to insert the vias manually (CADENCE auto-insertion apparently gives
problems)
1-2 weeks for routing (manual routing for controlled impedance traces plus
auto-routing)
1 week for final checks and generation of paperwork for manufacturing data
Completion date - between 3 and 4.5 weeks from now
Progress will be monitored closely as this module is on the critical path.
b) LVDS daughter-cards status
Richard reported that the bare boards would be ready by 13th May, when they
would go out for assembly (1 week). They should then be available by Monday
24th May for Richard to carry out simple checks with a basic test jig
(power, clocks, etc).
c) G-link daughter-cards status
Tony reported on behalf of Bob, who was on leave, that the Rx boards would
be ready early in the week beginning 17th May. The Tx board layout is
currently on hold, with placement partially complete, as the designer is
now working on the DSS mother-board layout.

3. ASIC designs:
a) Serialising ASIC/FPGA?
Viraj reported some extremely encouraging results from Ian's simulation
work. He has managed to get the smallest Xilinx VIRTEX FPGA to run in
simulation at 173 MHz, without using any special optimisation tricks. It
was noted that the particular device Ian has been targeting was speed grade
-5 (mid-range), and the use of speed grade -6 should raise the maximum
speed further. Pricing has been requested for 100-off and 2000-off
quantities. At present, the latency is 3 ticks (c.f. 2 ticks for the ASIC
simulation), but this is due to an extra latch stage which can almost
certainly be removed.
As the current firmware significantly under-utilises the gate capacity of
even the smallest VIRTEX device it may well be possible to double the
number of channels per device, accepting 40 rather than 20 input bits,
thereby halving the number of devices per CPM (savings in cost, power and
real-estate). Clearly, there would be a trade-off between halving the
number of packages and the possible need for a larger package. Ian will
look into these questions.
Assuming sufficiently low costs, the use of VIRTEX devices would remove all
NRE charges and risk factors associated with ASIC design, so would be a
very attractive alternative.
b) CP ASIC status and schedule
Encouraged by the above simulation results, there was some discussion about
the possibility of targeting the CP ASIC design into a larger VIRTEX
device. It is too early at this stage to assess the feasibility - Viraj
noted that issues of gate count and latency would have to be carefully
evaluated given a VHDL model. James will start to design the model as part
of the first draft of the specifications document.
It was decided to involve Alan in writing the precise definition of the
processing algorithms. It was thought that the use of software to translate
C code into VHDL would be very important, and at least one suitable
commercial package has already been identified. This will be followed up
further.

4. CPM prototype:
a) Update
Richard's draft 0 specifications document raised a number of interesting
points, which were discussed following the meeting. The total number of
backplane pins, assuming all I/O via the backplane (including PreProcessor
links and trigger multiplicity bits), would require a high module insertion
force.
Richard would also like to get some estimates of ASIC power consumption.
ACTION: Estimate maximum power consumption of Serialising and CP ASICs (and
FPGAs) - Viraj

5. Software for DSS link tests
Norman reported that Bill is now testing the new DAQ software with real
hardware, and preparations for the forthcoming DSS/link system tests are
progressing well.

6. Alternative options for pcb design
Richard reported that generally there are possibilities of getting layout
work done at CERN, although at present the system is somewhat overloaded.
He does not yet know the cost implications.
ACTION: Obtain details of costs for pcb layout work at CERN - Richard
ACTION: Investigate pcb facilities available to Space Science people at
Birmingham University - Richard

7. Current status of reviews
Tony summarised the current situation. The DSS system (motherboard and two
daughter-card designs) is awaiting a PDR concluding summary. The ROD
prototype specifications are still incomplete, with data format and buffer
management details remaining to be decided. The review of the Serialising
ASIC design specifications revealed serious deficiencies in the treatment
of BC-multiplexed data for DAQ, which are currently being urgently
addressed. The points raised by the PreProcessor ASIC PDR were
comprehensively addressed by Paul Hanke et al, and only a very small number
of outstanding issues remain, which it is hoped can be cleared up soon by a
telephone conference call. Finally, the CCM prototype specifications
document (version draft 4.0) is now on the Web
(hepnts1.rl.ac.uk/Atlas-L1/Modules/Modules.html), and the four reviewers
have been notified. It is hoped to carry out the review at the beginning of
June - probably by means of a tele-conference.

8. Any other business
Viraj noted that he now has the S-link cards, together with the User Manual
which indicates that the upper limit for operation is only 80 Mbyte/s,
whereas our requirement is for at least 100 Mbyte/s. This must be
understood.

* Next meeting - Tuesday 18th May at 14.00, room Q12 in the Poynting
Building, Birmingham University.
N.B. This was the room used on the last day of the Joint Level-1 Meeting in
March 1999.

Tony Gillman