ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 20 July 1999

Minutes

Present: Eric Eisenhandler, Norman Gee, Tony Gillman, Bob Hatley, Viraj
Perera

1. DSS system
a) DSS motherboard status
Viraj reported that the layout is now complete, and the paperwork will
be finished for the board to go out for manufacture (6 off) and assembly
by 21st July. As it is running very late, we will pay the additional
premium for a 10-day turnaround. This will mean that we will receive
assembled boards back at RAL for stand-alone tests by mid- August. After
basic testing in ID, the boards would be exercised with Kithsiri's
diagnostic software in Lab 12. It was noted that the necessary hardware
infrastructure must be ready before mid-August - workstation/pc,
monitor, VME crate, etc. Tested boards should then be available for
Richard et al to carry out system tests at Birmingham starting at the
beginning of September. Timescales should be more 
predictable from now, as the manufacturing route is well-established.
Eric will re-check people's availability from August onwards.

b) Cable assemblies
There was some discussion of the options available to us for different
cable assemblies. It was generally agreed that only halogen-free cable
should be used in the tests. In Richard's absence it was decided to have
a phone conference with him after the meeting to agree a plan. The
outcome was:
i) Richard will send details of the flexible Cat 5 (6?) AMP cable, from
which we have already made some 2m patch cable assemblies, to the
appropriate CERN safety people to ask if it will be acceptable for use
in USA15. 
ii) If OK, Bob will order ~50m of this cable and Richard will arrange
for a Birmingham technician to make up assemblies of lengths 6m, 8m,
10m, 12m, 14m and 16m (one of each length), for tests to scan for
maximum cable length. 
iii) Bob will also check the specifications of the shielded twisted-pair
cable, held in the CERN Stores, that will be used to bring the LAr
trigger tower signals from the detector, and which may also be suitable
for our application. 

b) TDR measurements on JEM-2 LVDS traces
Tony reminded the meeting that at the recent Joint Meeting we had
offered to try to measure the impedances of the long traces on the JEM-2
boards, as mismatches with the 100-ohm cables may be the cause of LVDS
link errors seen when board traces were included in the link path. Viraj
will check if appropriate instrumentation (very fast risetime pulser,
etc.) exists in ID. 

2. ROD prototype - update. Next stage?
Viraj reported that the revised specifications document was essentially
complete, and James had started to look at partitioning the various
functions between FPGAs. Viraj proposed holding a meeting on 21st July
to highlight and discuss the changes that have been made since the
review. The overall timescale for the module had obviously slipped
considerably since the beginning of the year, and the current schedule
shows manufacture not before the end of 1999. 

3. TCM prototype programme - update
(Note that the TCM (Timing and Control module) is the new approved name
for the CCM!) The review concluded at the end of June, and the revised
(final) specifications document is almost ready for putting on the Web,
together with the review summary which has now been written. The aim is
to have the final material on the Web by the end of July. Bob requires
several pieces of information regarding the TTCrx chip, most of which
were obtained from Philippe Farthouat at the recent Level-1 Workshop.
Tony will e- mail Philippe for the remaining answers. 

4. CP ASIC specifications - update
Progress in this area has been delayed due to other more urgent issues,
but it will now pick up again. It is becoming more urgent, as its
precise specifications will soon be needed for the CPM prototype. So
far, Viraj only has a basic draft framework of the specifications
document, and the next stage is for Alan to work with him to specify the
algorithms. It is now expected that the PDR for this component will not
be until the end of 1999.

5. CPM prototype specifications - update
In Richard's absence there was little discussion of this module. He has
already written a draft document which covers a lot of material, but
there are still some "holes" to be filled in. It was noted that final
specifications could not be completed before the LVDS/G-link decision
was made, and also not until the CP ASIC was fully-specified. If we are
to use a common HCM across the CP and JEP prototype systems, then we
should preferably use identical crate sizes and backplane connectors
(assuming an in- crate HCM architecture). At present, the CPM is planned
to be 9U, with BERG 5-row connectors, and the JEM is planned to be 6U
with AMP 7-row connectors! Close and frequent consultation between the
two processor communities is essential. 

6. HCM - update. Next stage?
(Note that the HCM (Hit Counting module) is the new approved name for
the CMM!) Norman reminded the meeting that there is a draft document
outlining the basic functionality of the module. The next stage will be
to write a full specification which will then be subject to review.
Although we had not originally intended to design a prototype module it
was now felt that this would be a good idea, and matched well with an
overall prototype programme. It was realised that we had not discussed
where this module might be designed and built - this should be resolved
soon. 

7. Any other business
It was noted that the JEM-1 prototype system modules (JEM, SMM and HCM)
were at present not subject to any review process. Tony will contact Uli
and Sam to suggest that we should start planning a review procedure for
them. 

* Next meeting - Tuesday 27th July at 11.00 in CR02, R1 at RAL.

Tony Gillman