ATLAS Level-1 Calorimeter Trigger

Hardware Progress Meeting - 22 June 1999


Minutes


Present: Ian Brawn, Eric Eisenhandler, Tony Gillman, Kithsiri
Jayananda, Viraj Perera, Richard Staley


1. ACTION list from previous meeting (18-5-1999):

a) Richard was again encouraged to release his write-up on the
backplane transmission studies as an ATLAS note, so he will try to do
this as soon as possible.

b) Richard has obtained some figures for the cost of pcb layout via
CERN. A "typical" 6U VME board (6 layers) cost <<£900 ~1 year ago. It
would help if a job were presented as a CERN project - i.e. as an ATLAS
level-1 design. We would need to be certain that the layout people used
CADENCE, for compatibility with our schematic designs.

c) Richard has started to look into the pcb layout facilities available
in Birmingham's Space Science Department, but nothing yet to report.


2. DSS system:

a) DSS motherboard layout status

Viraj reported that the layout is still under way, but the worst is
almost certainly past, with no potential show-stoppers now likely. All
except 24 traces have now been successfully routed using the new fast
auto-router, including ~200 controlled impedance (75 ohm) 100 micron
wide. The remaining 24 traces are now being routed manually, and the
final layout is expected to be completed in just over two weeks from
now. Allowing the usual three weeks for board manufacture and assembly
this should give us assembled boards for test by the end of July.
Allowing a week or so for preliminary stand-alone tests we would hope
to start the full-scale link system tests in Birmingham by mid-August.
We will check people's availability around this time.=20

b) LVDS daughter-cards status

Richard reported that he has successfully operated these cards at up to
50 MHz and with power supplies down to 2.6V, with perfect lock being
achieved routinely. The Tx and Rx cards were connected "back-to-back"
via a feedthrough connector, and power/control and clocks fed in via a
test card. The results can be found on Richard's Web-page
(www.ep.ph.bham.ac.uk/user/staley).

c) G-link daughter-cards status

Tony reported on behalf of Bob, who was on leave, that the Rx boards
have been available for some weeks, but cannot easily be tested without
their Tx partners and/or a DSS mother-board. The Tx board layout is
currently on hold, with placement complete, as the designer is now
working on the DSS mother-board layout. Another 1-2 weeks is required
to complete the layout, once the designer is free.

d) Cable assemblies

Tony reported that Bob has drawn up a list of varying length cable
assemblies, but there are problems getting them made, as a special
manual assembly tool is required which seems to be difficult to obtain.
This is being pursued at RAL, but a fall-back solution would be to
assemble the cables by hand - tedious but believed acceptable. There is
a technician available in an outside company to do this work if
necessary.

e) Software for link tests

Kithsiri reported that he has almost completed a full User Guide to the
DSS diagnostic software, which he will put on the Web when complete.

It is believed that the DAQ software is progressing well.

f) Tentative schedule for link tests

Tony reported that it would seem unlikely that we shall have completed
the full-scale tests until September this year. It was suggested that
the Exploitation Plan for these tests should be finalised and put on
the Web, for general scrutiny.


3. ROD prototype update:

Viraj reported that there was only one outstanding issue now to be
resolved before the final post-review specifications document could be
released. This concerned the data format from the CPM MUX FPGA - does
it need to be zero-suppressed or not? Only if five or more time-slices
need to be recorded at the full L1A rate would we need
zero-suppression, and it is not clear that this is really necessary. It
would add significant complexity to the CPM MUX FPGAs and the ROD
FPGAs. As this is a prototype module, we decided that it might be
useful to design two versions of the FPGA code to handle data with and
without zero-suppression. This issue should be discussed further at the
next Joint Meeting.


4. "ASIC" designs:

a) Serialising (MUX) FPGA status

Ian has been exploring the possibility of doubling the channel density
of the Serialising FPGA (henceforth re-named the MUX FPGA). He finds
that using the 50K-gate VIRTEX device the gate utilisation would be
close to 100%, which is not viable. However, moving to the next size
device (100K gates) would increase costs by only a small factor (actual
figure not to hand, but much less than two), so this would be an
economical solution, as well as significantly reducing the CPM board
real-estate (half the number of packages).

Regarding the specifications document, most of the post-review changes
have now been incorporated but the remaining issue is that of the need
(or not) for zero-suppression on the DAQ data feeding the ROD (see
above comments).

b) CP ASIC (FPGA?) update

Viraj reported that there has not been very much progress recently in
this area, although he has a very preliminary draft 0 specifications
document. He and Alan will discuss the algorithm specifications as soon
as Alan's exam load is over. The most interesting possibility is the
replacement of the ASIC with a large, fast FPGA, but this will not be
addressed until the VHDL model is constructed following the full
specifications. One important consideration will be latency, which may
well increase with an FPGA implementation. Any cost/benefit trade-offs
of this nature may have to be brought to the T/DAQ Steering Group.



5. CPM prototype specifications update:

Richard reported that the worrying issue of high module insertion force
(~370 N) discussed at the last group meeting has been solved. By using
backplane connector sections with three different pin lengths (standard
off-the-shelf issue) the insertion force could be reduced to ~240 N,
which would be entirely acceptable. An added benefit is that this
staggered insertion can be designed to improve protection against
static.

Richard was asked to draw up preliminary floor-plans for the final and
prototype CPMs, in order to demonstrate that MCMs would be unnecessary
(assuming LVDS is the chosen link technology). The LVDS receiver chips
are sufficiently low profile to allow double-sided board mounting if
necessary, and cooling would not be a problem.


6. CCM prototype programme:

Viraj reported that Bob will design the TTC Receiver-Fanout
daughter-card, which will accept an optical input from the TTCvx and
produce multiple electrical TTC signals via cable connectors for
driving the prototype trigger modules. Kevin has almost completed the
layout of the daughter-card for initial use with the old TCM - this
will go out for manufacture very soon. The CAN-bus kit system now works
- data can be correctly transferred. With the departure of the YII
student, Bob will gradually become involved in this part of the CCM
prototype programme. It is proposed to design the CPM and ROD
prototypes to incorporate CAN-bus nodes, so that the system can be
evaluated in earnest.

Part of the CCM prototype system review has already taken place, and it
will hopefully conclude on Friday 25th June.


7. CMM backplane simulations update:

Kithsiri reported that he has had to suspend this work as the problems
he was encountering have had to be referred to experts at CADENCE. The
formal procedure unfortunately requires relaying the queries via the
appropriate RAL contact person, so no direct discussions can be held.
So far almost one month has elapsed since CADENCE were first approached. 
Philippe Farthouat has suggested a couple of names of ATLAS people
who have experience of CADENCE simulation tools and may be able to
help. Kithsiri will try to contact them. Also, it was proposed at the
meeting that it may be useful for Kithsiri to contact Ullrich Pfeiffer
who may have similar experience.

8. Any other business:

Eric raised the question about who would be attending the level-1
workshop at CERN on July 14-16, and what might be presented. He
suggested a few possible topics to consider:

i) Changes to the CP architecture and technologies

ii) Replacement of ASICs by FPGAs - using the MUX FPGA as a specific
example

iii) The relative merits of LVDS and G-link technologies

iv) Results from backplane transmission studies

v) Achievement of reduced module insertion forces


Richard mentioned that he had obtained details of halogen-free cable
suitable for our inter-crate links, from a company named Tensolite. The
cost was £2.40 per metre for a 4 twisted-pair cable bundle (c.f. £1.30
per metre for AMP Category 6 cable, and £6.20 per metre for GORE cable
- neither halogen-free). However, the minimum order quantity would be
5000 feet, at a cost of $4250, and unfortunately samples are not
available.


* Next meeting - Tuesday 6th July at 11.00 in CR01, R1 at RAL.


Tony Gillman