Minutes of the ATLAS-UK Level-1 Calorimeter Trigger Meeting Friday 19th March 1999 Present: Eric Eisenhandler, Tony Gillman, Bob Hatley, Norman Gee, Paul Bright-Thomas, Ian Brawn, Azmat Shah, James Edwards, Viraj Perera, John Garvey, Murrough Landon, Bill Stokes, Richard Staley, Kithsiri Jayananda Bunch crossing identification and calorimeter signals - Paul Bright-Thomas Paul discussed his studies with Pspice modelling of liquid Ar EM pulse shapes. At zero eta, signals saturate above 300 Gev. At 2.5 eta they saturate at about 200 Gev. After normalisation of low Et pulse shapes, one can see variations in their duration. Pulses that saturate are not properly treated in the simulation. The normalised pulses were sent through the FIR filter BCID simulation. The efficiency of BCID was low for very small pulses. After 4 Gev, efficiency was almost 100% for all eta values. An efficiency degradation was also observed (about 5%) for broader pulses. Further improvements to model are still needed. Results of Edge BCID were also described. Using only one threshold, it failed at high Et and was over-sensitive to width variations. Although good with ideal pulses, this scheme did not work well with real pulses with time jitter. However, the results were good when s-2 samples and a second threshold were included. Paul said that attempts to obtain better data on calorimeter pulse shapes had been unsuccessful. Tools for FPGA design - James Edwards James made a presentation of the tools used in FPGA design. The tools used are Renoir, Modelsim and Leonardo. Use of them was explained taking the design of a pedestrian crossing system as an example. The first step is to use Renoir to implement the concept using state machines, VHDL code or block diagrams. After that simulated results can be seen in various forms, including wave forms. The output of Renoir, the final VHDL code, is used by Leonardo to implement the code in the selected target device. The possibility of using some of the information generated by Renoir for documentation was discussed. Norman asked whether it will be possible to recheck the design many years later if it becomes necessary. Viraj said that files generated by the tools will be archived and will be available. Paul pointed out that the implementation of an algorithm that only existed as a Fortran code is not very straightforward and errors could creep in. Viraj mentioned that C to VHDL converters exist and Eric said that Fortran to C converters also exit. Therefore it should be possible in theory. However, this chain of conversions could result in inefficient final designs. Because the algorithms are not extremely complicated it should be easy to write them in C directly. Tony asked how the libraries for new devices are found. Normally they become available with new versions of tools. Before that, it is possible obtain them from the manufacturers of devices. Status of back plane transmission tests - Richard Staley Tests were done using boards that can act as sources and/or sinks for CMOS and GTL signals through a back plane connector. CMOS devices from Fairchild VCX family and GTL devices from Texas Inst. GTL+ family were tested. Error rate vs. receiver clock phase was studied with adjacent channels driven together with alternating zeros and ones at 160Mb/s. In CMOS back planes the signals were good. There were no errors after 5 minutes for delays up to 3.1 ns with or without signals in adjacent channels. But with GTL, there were continuous errors for all delay settings if adjacent channels were running. They ran very hot too. More studies will be carried out on CMOS by running BER tests overnight and by powering them from lower supply voltages. Status of DSS motherboard - Viraj Perera Specifications are now ready to go on the web. FPGA design has been finished by James. TTC receiver schematic is also compete and S-Link is partially complete. VME interface is being simulated and will take one or two days. The full design will be complete in less than two weeks. Status of LVDS daughter cards for DSS - Richard Staley Receiver cards are now in drawing office. They will take about a week. Transmission cards are in the drawing office but not yet being worked on. Status of G-Link daughter cards for DSS - Bob Hatley G-link daughter card specification is ready to go to web. Schematics are waiting to be sent to the drawing office. Norman - Exploitation plan Norman described an exploitation plan for the DSS, a list of tests to be carried out with a nominally working DSS module, to determine whether it does exactly what it is supposed to do. Tests with LVDS will be carried out first. It will involve testing with a number of different cable lengths, running overnight, testing with worst case situations such as with bundled cables and running with modules in the same crate and in different crates. After that similar tests will be carried out with G-Link and S-Link daughter boards. Tony mentioned that all tests listed may not be needed for all daughter cards. Eric said that in some cases checking for extreme conditions may be enough. Some short cuts will be necessary to reduce amount of time spent on the tests. Kithsiri - DSS diagnostic software Implementation of all registers and memory buffers in diagnostic software has been completed. A few things like cleaning up of the code and adding some documentation are left. Norman said that some VME tests can be carried out after incorporating DSS part of the code with Murrough's new version of diagnostics. Murrough said that he will attend to it next week. DAQ software for DSS - Bill Stokes Reading registers and memory is possible. Appropriate menus exist. What is left is tidying up some of the code and adding histograms. Need to talk to Norman about the format of data from the DSS. Clock control module - Viraj Perera Optical TTC input into the CCM will only be possible in the final stage. It is planned to use a CERN built interface module before the final stage. Four TTCrx cards have been purchased from CERN already. However they cannot be used until TTCvx becomes available in June. TTCvi is already available. Therefore another module with the same foot print as CERN modules has been designed as an interim solution, using inputs from the present TCM. Murrough asked whether documentation on accessing these modules through software were available. The answer was yes. Eric said that some documentation, preferably a diagram, to explain how these modules are to be used as an interim solution would be useful. Bob also expressed the need for a document or a block diagram. Murrough asked how the DSS will be connected to the CCM in the final system, if it becomes necessary to carry out any tests. Viraj said that signals will be available from the back plane of CPM, both in electrical and optical form. They will have to be plugged into the DSS at the front panel. ROD status - Viraj Perera Viraj Described changes made to the PDR. Details which were missing in the previous version have been added. There are some items, including data formats, that needed to be clarified and defined. Norman said that he has a list of items to be sorted out through discussion. If certain items still remain undefined it may be necessary to go ahead without them. As this is still a prototype such things can be tolerated up to a certain extent. It was decided to have more discussions on ROD. Serialising ASIC - Ian Brawn Waiting for post synthesis on Chip Express. Enough information on Virtex devices are not available yet. The cost is not known either. It will take one or two weeks. Cluster Merger Module and common design - Norman Gee Norman Described the results of a discussion held with Stockholm group at Birmingham. A hand drawn diagram of the JEM crate back plane is now available. In TDR it is proposed to carry input signals to CMMs through cables while input signals for JMMs are to be carried via back plane. The discussion was for adopting a common back plane scheme for both. Stockholm agreed to change designs so that ROD data from JEP will not go through JMM, but via the SMM and then through G-Links to RODs. In current design of JEM backplane 40MHz signals need to be carried through the entire length of the back plane. A simulation is required to make sure that it is feasible. Kithsiri is willing to carry out the simulation. A proper diagram of the back plane has to be drawn before that. As a response to a question asked by Tony, Norman mentioned that there are not be enough pins in JEP crates for all energy sum signals if it is run at 40MHz and therefore it may be necessary to run it at 80 MHz. Finally both systems should use the same speed. Summary of reviews status - Tony Gillman Reviews of DSS motherboard and daughter boards are now complete. Specifications of the ROD prototype are being modified. Discussions with the designers of the PPrASIC have been started. There are some delays in the SASIC. Final documents of all of them will be available on web by the end of March. Tony outlined some measures to be incorporated in future reviews for avoiding problems experienced with the current ones. Software status - Murrough Landon Murrough has down loaded Cornelius's software for testing. Some work is needed for compiling it in his machine. A decision will have to be taken whether to continue with existing diagnostics system or to adopt Cornelius's software. Eric reminded about the question of upgrading hardware. Norman said that one PC will be bought very soon to be used as an X terminal for DSS tests. Initially it will run NT and if necessary Linux can be installed later. Progress on unified costing - Norman Gee Norman mentioned that there is confusion about what should go as core expenses and what should not. More discussions are needed. TDR upgrade page for web - Norman Gee Norman has already done some work. He has categorised changes as algorithmic, technological and architectural. Each entry in the web will contain the TDR page number, a description of the changes, why the change was necessary and whether it was agreed or not. Eric said that some diagrams have changed too and use of the EDMS system should be considered at some stage. Next meeting: It was tentatively agreed to have the next meeting on 26th April.