ATLAS-UK Level-1 Calorimeter Trigger meeting ============================================ Wednesday 20 January 1999 - Birmingham Present: Tony Gillman, Kithsiri Jayananda, Richard Staley, Bob Hatley, Alan Watson, Scott Talbot (minutes), Richard Keeler, Paul Bright- Thomas, Norman Gee, Viraj Perera, Ian Brawn, John Garvey, Reg Gibson, Tara Shah, Pete Watkins, Eric Eisenhandler Data transmission ----------------- Backplane tests - Richard S --------------------------- Richard presented the plans for the backplane tests, using both GTL and CMOS. The test will be done entirely on the board, using PLDs, so no software will be needed. The board design was sent out today and should be back in 2 weeks (not 3 as on transparencies), then 1 week for assembly. Paul asked if 200 Mb/s tests could be done. Richard wasn't sure if the PLD's would be fast enough. Data source/sink test module - Viraj/Tony/Richard ------------------------------------------------- Although the DSS module is mainly for ROD tests with customised daughterboards it can be used for several tests. The source can be programmed to generate different data sets, and the sink can record, compare and detect errors. The module can be used for both stand-alone and multiple tests The module specification has been reviewed by the panel and will be released for all to see. The PDR should be completed later this month, with the FDR in February. Tests should begin in April. There will be three daughter cards, one off the shelf and one each for LVDS (designed by Richard) and G-link (designed by Bob). Four motherboards will be made, along with four pairs of LVDS daughter- cards, and one pair each of G-link and S-link. The LVDS adds framing complications for the ROD link, and so might not be used for that purpose. Tara asked whether this means that LVDS will never completely replace G-link. It could do so, but in it not essential in this case. Richard showed the plans for the daughter boards. The front panel connections will uses standard parts with the cables made by the manufacturer. Richard confirmed that the design has enough pins for the final CPM. The electrical interface with the DSS can scan timings. Hardware status --------------- Overview - Viraj ---------------- We are involved in four module designs - Cluster Processor Module, Cluster Merger Module, Readout Driver, Clock Control Module - as well as the backplane, multi-chip module, two ASICs (serialising and cluster- processing), and the test module (DSS). The CMM might be done in common for the CP and JEP. This involves a decision on whether it's in the crate or not, which in turn requires a simulation of the backplanes. This simulation of the backplanes is not yet allocated and may be done at Stockholm or RAL. The ASICs can be designed to handle G-link and LVDS, but the I/O technologies can't be decided until the tests are finished. For the serialising ASIC a choice between CMOS and GTL on the backplane is also needed. The specification for the serialising ASIC is about 80% done. The specification for the CP ASIC will be written soon. Nothing is done for the CPM yet and the MCM is on hold until the decision whether to use G-link or LVDS is made. If LVDS is chosen, the MCM will become a hybrid, which would be larger but with a lower risk factor. No components will be "plug-in" replaceable because they are surface- mount, but there will be enough spares available and components can be replaced by skilled people using the right equipment. CCM - Viraj ----------- Two CERN TTC test modules are available and will be used in the tests. Both optical and electronic signal tests will be done. The CCM fans TTC signals out electrically to TTCrx chips on the modules via the backplane. (This has changed since the TDR.) The CCM tests will use small plug-in cards to test the various components. The TCM will only be needed while the TTC is being commissioned. The interface to the DCS will initially plug into the CAN bus. As the CAN bus is used throughout ATLAS there should eventually be standard software. The CCM also has to interface with the CTP to send busy signals. The specification document is almost complete with a PDR in February, FDR in March and tests starting in April. ROD - Viraj ----------- The ROD collects data from several trigger processing modules, and the timing delays from each will have to be determined in advance. The prototype has four channels, and needs the DSS module for testing - inputs on G-link, outputs on S-link. As the monitoring hasn't been decided yet the board is being designed to see how good the design is. The specification is essentially done. The PDR is very soon, with the FDR in March/April and tests beginning in May/June. Serialising ASIC - Ian ---------------------- The specification won't be finalised for a couple of weeks. A VHDL design to evaluate the 0.35 um Chip Express gate array technology is being done. Review of Hardware - Tony -------------------------- The is little change since the Heidelberg meeting. The preprocessor ASIC specification should be available next week, and the PDR is being set up. There are 15 hardware PDRs in the next two years, eight of which are by April. The members of the first four review groups, and dates, were suggested. Documents will be made available publicly, but to ensure that the timescale is met, "outside" comments on the PDR should only be sent to one of the nominated people on the review panel. In order to monitor progress, brief weekly engineering meetings will be held. Summaries will be made available on the Web. Richard then presented the status and plans for the Birmingham Trigger lab facilities, but wasn't sure whether the installed Xilinx tools are compatible with those at RAL. Simulation ---------- Alan had little to say on the E.M. & tau thresholds, RoIs, etc, as more physics check ares needed. The overlap between the offline and online monitoring software and the trigger performance simulation software was discussed. The online and offline monitoring code are expected to be similar although the online may have a lot of extra detail. The offline code is expected to be available first, but the transition from FORTRAN to C++ still has to be done. How much overlap there is with the simulation is not clear. BCID and calorimeter signals ---------------------------- BCID - Paul ----------- Paul has been looking at the implementation of the leading edge BCID suggested by Ullrich at Heidelberg, and showed one way to implement it. More study is needed, especially at E_T > 1 TeV. PSPICE simulation - Richard K ---------------------------- The software has arrived at Birmingham and will be installed on a new PC soon. Scott is also looking at the software as Richard is only at Birmingham for a couple more months. Richard also added that the HEC trigger electronics has moved from Montreal to somewhere in Russia. FCAL/TileCal status - Eric/Paul ------------------------------- Eric interpreted the current status of the FCAL from the recent emails. There are still more signals than stated in the TDR, but the signals will be converted to E_T before we receive them and the hadronic ones will be summed over the full depth of FCAL2 and FCAL3. Paul raised concerns about the consistency in the pulse shape and rise time. From earlier tests Alan doesn't think the reduced phi granularity will be a problem, but a spatial trigger will not be possible. Paul has no news about the TileCal yet. Software -------- Software status - Norman ------------------------ The software group meets once a month and is looking at various code management tools, the software requirements and the DAQ -1 software. The decision whether to modify the existing code or produce something new for the DSS/ROD hardware tests will be taken after the software specifications have been decided. This will be done by the next meeting in February. Miscellaneous ------------- John summarised the visit to CERN by the UK Science Minister on 15 Jan. When more information about the ATLAS week is available a decision whether to hold a software meeting will be taken. The next joint meeting is in Birmingham between 4-6 March. Pete Watkins is the contact person. There may be a software meeting on Thursday morning. The Management Committee will meet on Thursday evening, and the group meal will be on Friday. A draft bulletin will be sent out soon. Norman is working on the costing and hopes to have it ready by ATLAS week. The new web pages are almost ready (still need some updating). They are on Windows NT and should be edited with FrontPage. This will allow access by more people, so the updating load can be shared. ***************************************************** The next UK meeting will be on Friday 19 March at RAL