ATLAS-UK Level-1 Calorimeter Trigger Meeting Monday 26th April 1999, Rutherford Appleton Laboratory The minutes of previous UK meeting are not on the web yet, Norman will put them on soon. Bunch-crossing identification and calorimeter signals ===================================================== TileCal trigger-sum electronics review - Paul --------------------------------------------- On 23/24 April the TileCal group had an electronics review. The first session was dedicated to trigger sums. It began with a short history. The Discrete transistor is OK, but has poor recovery from overload. The WTA (Wideband Transconductance Amplifier) prototype, with unity gain and single input, had lab tests and testbeam in 1998. The "final version" WTA, with x8 gain and 6 inputs, had lab tests last week. With the current gain the output will saturate at an equivalent of 500 GeV in E, which limits the dynamic range in E_t and may need revising. Alan quickly calculated that reducing the gain to x7 wouldn't cause any problems. During the TileCal review it was suggested that the number of inputs could be reduced to 5 as only the boundaries of the detector would ever use the sixth input. This decision would need input from us. After some discussion it was decided that summing six inputs together has little effect and would cause us too much trouble to reduce to 5. A note will be sent to the TileCal group saying we want the number of inputs left at 6. Overall the amplifier has fast overload recovery and all channels are differential so there is good noise reduction. Signals from the 3rd layer will be sent directly to the muon trigger. There is a SPICE model for both the adder and the 3-in-1 board available. The labtests and SPICE simulation of the adder shows good pulse shape. Paul will obtain both SPICE models and run a simulation of the whole chain. The Rio group has some decent web pages available - http://www.lacc.ufrj.br/~cern/Summation/index.html There will be a redesign for the TileCal test beam in July, with a review in September, production in November and delivery in March. No radiation tests have been performed yet, nor have they thought fully about grounding, cabling, connectors. Alan asked whether the cell C9 should have the same weight as the rest of the detector as it is basically a presampler. Norman asked about what would happen if some inputs were fine for them but too noisy for us. We need to find out exactly how the switches to turn off any noisy input work, since no one knew for certain. SPICE simulation - Paul ----------------------- Paul and Richard K have tested the current SPICE model for the ECAL and have been working on improving the design of the simulation to allow multiple channels to be added, the saturation levels have been corrected, and it's been made more modular. This work will continue this week. At the end of the week Richard leaves Birmingham, but he will still answer email. Data transmission ================= Status of backplane transmission tests - Tony for Richard S ----------------------------------------------------------- Richard Staley couldn't make the meeting so Tony gave a brief summary. At Birmingham Richard has CMOS cards running with adequate timing margins of 4 ns at 2V and a low error rate of < 2x10^13. GTL simply does not seem to work at 160 Mb/s. He is writing the details up. Status of DSS mother & daughter cards - James/Richard/Bob --------------------------------------------------------- James reported that the motherboard schematics should be completed by the end of the week and sent to the Drawing Office for layout. Viraj has checked the schematics and corrected some minor errors. Murrough asked about the FPGA downloading. It appears that it is only one bit at a time and he worried that this is going to be too slow. The LVDS daughter card left the drawing office for manufacture at the end of last week and should come back in about 3 weeks. The connectors have been ordered and should arrive before the motherboard. A test rig might be lashed together instead of waiting for the motherboard. The G-link receiver design and layout is completed and is being checked. Assuming there are no problems the order will go out tomorrow (27 April) with a 2 week turn around. The transmitter layout is being completed, but the timing depends on what happens with the motherboard. Heidelberg are now making their own G-link card due to the delay. The motherboard is now very late and so the drawing office will be encouraged to speed up and the production will be sped up by paying extra. Exploitation plan for LVDS tests - Norman ----------------------------------------- The boards will be subjected to engineering tests before reaching us. The diagnostics will test the individual registers and when the motherboard and daughter boards work the LVDS testing will start. A draft of the tests we will perform is available, an update will be ready soon. Diagnostic software for LVDS tests - Kithsiri --------------------------------------------- The diagnostic software is written and uses 3 windows to show the ~60 registers, and 3 windows for the memory. The software has been tested with a memory board and a minor problem with the "Verify" option has been found. It shouldn't take too long to fix. DAQ software for LVDS tests - Bill ---------------------------------- The software for the menu system and producer is written and debugged. It still needs to be tested, but the memory board at Birmingham has a few problems. When the code is tested it will be cleaned up to remove the obsolete modules. The LynxOS system at Birmingham is now visible from RAL and Murrough needs to check it is visible from QMW. Hardware status summaries ========================= Clock control module - Viraj ---------------------------- Draft 4 has gone out to the review panel and will be put on the web. ROD - Viraj and Norman ---------------------- There are a couple of outstanding issues: Trigger type - it had been suggested that there would be different event lengths for the different triggers. It is now decided that long events (5 slices) will always be sent tot the ROD. The ROD will then sort out the details. Data format - The DAQ format is not defined for jets, although the RoI format is. Our formats are probably understood, but still need to be pinned down. Without data compression the ROD cannot cope with output of even one slice The LVL2 interface is under discussion. They would like to remove the event header. In summary, Some of the specs are complete but others are still being discussed. Murrough suggested that for early debugging, we might want to forget about deadtime and read out a large number of slices. It was decided that this would be too much work and in any case is not compatible with the Preprocessor, which can only read out five BCs. The general issue with the ROD is what the prototype is for and when we need it. Contrary to previous conclusions, it is now felt that it should include roughly the full functionality of the final ROD. Serialising ASIC - Ian ---------------------- The PDR is done and raised several issues: 1) Uses 2 clocks, G-link source driving the real time data and LHC clock driving readout. This means there is a danger of timing violation, and what happens if the G-link clock is lost? 2) How to decode the BC multiplexing for DAQ? The forthcoming new specs will address these. Realtime data and timing simulation tests have been performed using the Xillinx Virtex FPGA. It doesn't run at 160MHz yet (only 131 MHz). So more investigation is needed. Common merger module progress - Norman -------------------------------------- We and the Jet people are interested in this. There are 2 possibilities - transmitting over the backplane to modules in the same crate, or over cables to modules in a separate crate. Kithsiri has started a simulation of the backplane method, which is the preferred solution, and hopefully this will be completed in a few weeks. If wanted then some of the CMM specs could be written without detailed description of the input. Summary of reviews status - Tony -------------------------------- The PPrASIC has been comprehensively reviewed and every point addressed (23 page document available on the web). The majority of the points have been satisfactorily answered with some additions to text, etc. to help understanding. There are a few issues left: - Best way to communicate saturated tower data to CP and JEM systems. - Loading/readout of ASICs fast enough. - Adding scrolling diagnostic memory to final output data into CP and JEM. - Error handling. - Use of inter bunch gaps for test data. Try to resolve these as soon as possible. The DSS review consisted of 3 individual reviews and a large number of points were raised, most asking for clarification. The general architecture is sound. A large number of issues were related to the programming model which needed tidying up. A few Hardware issues and led to an improved FPGA configuration, an improved termination scheme for the transmission lines between the mother and daughter boards and some minor changes to the G-link card design which could allow it to be used in the Heidelberg test system. Overall the spec have been updated with no unresolved issues, and a summary will be put on the web soon. In the ROD review several serious omissions were uncovered: - How to handle the insertion of the late-arriving trigger type word into the event fragments. - How the event buffer is going to be managed - How are errors going to be handled - Format of the S-link data; it has to conform to ATLAS standards All these issues are being addressed. No timescale for concluding yet. Simulation and software ======================= Further work on e.m. and tau algorithms - Alan ---------------------------------------------- Using one RoI algoritm is simpler to implement and can make the EM and tau/h selections exclusive, but as it means using the tau/h algorithm there are some possible probems: - the RoI co-ordinate might be displaced by 0.1. This is not worrisome as the cluster would still be within the RoI. - the EM isolation sum might be increased, reducing the efficiency. Here the hadronic isolation is expected to be tighter than the EM isolation, so the events would be lost anyway. - the EM clusters E_t might be reduced. Here the magnitude of the effect would have to be smaller than the hadronic E_t deposit, and this is not too a big problem with the object likely to be selected Destructive testing of the effect of using a single algorithm by increasing the hadronic noise and using twice the nominal pile up showed no effect on physics and little difference in efficiency using one or two algoritms. This simulation should overestimate the effects. Alan is writing a note so this work can be aired to a wider audience. Software status report - Murrough --------------------------------- Little to say since software meeting on 19 Apr. No conclusion have been reached on future platforms or witht he DAQ-1 software. Out of the rut ============== FPGAs vs. ASICs - Ian --------------------- Ian gave a survey of some recent devices. FPGAs from Xilinx and Altera are now available with 1 million gates and at speeds up to 200 MHz. They are flexible and use familiar design tools, but Chip Express (and other ASIC vendors) will presumably be cheaper per part, once the NRE is paid. CTP review - Eric ----------------- The CTP PDR was on 7 Apr. There was no detailed design and the documentation was given in advance so the review was quick. There were 2 presentations and many of the recommendation from the last review have been implemented. Very impressive overall. Miscellaneous ============= There has been no progress on the unified costing. A TDR updates page is now available on the web, giving a reference to the TDR, a summary of the TDR version, and the proposed new version along with the status of the proposal. There is a new Trigger/DAQ steering group. It is much smaller than before, but experts will be called in as needed. It will meet next week and Eric will have to let them know that we have missed some milestones. The next ATLAS week is from 7 - 11 June and will be an overview. Everyone is encouraged to go, but try to get cheap flights. The next joint meeting will be at RAL from 1-3 July. As last time there will be a software meeting on the first morning. The level-1 workshop will be at CERN between 14-16 July. It will be of interest to the whole of level-1 and the 3rd day will be with CMS representative(s). There is little going to the LEB workshop and IEEE conference. Heidelberg will be sending two papers to LEB and one to IEEE. RAL will send one paper to LEB. Suggestions for other publications are welcome. AOB === Paul H, Bill Cleland and Paul B-T will be at SACLAY on 31 May and 1 June to make measurements of pulses coming from the LAr calorimeter module-0 electronics. ************************************************* * The next meeting will be on Wed 26 May at RAL * *************************************************