Minutes of the ATLAS-UK Level-1 Calorimeter Trigger Meeting RAL Wednesday 26 May 1999 Present: Eric Eisenhandler, Paul Bright-Thomas, Bob Hatley, Kithsiri Jayananda, John Garvey, Murrough Landon, Viraj Perera, Tony Gillman, Tara Shah, Bill Stokes, Richard Staley, Norman Gee, Ian Brawn, James Edwards, Scott Talbot Data Transmission ================= Status of backplane transmission tests - Richard Staley ------------------------------------------------------- Richard described the tests that had been done to test backplane transmission technologies. Full details can be found on the web (www.ep.ph.bham.ac.uk/user/staley/t_report.ps); Atlas Note to follow, comments welcome. Tests show that the Fairchild VCX CMOS devices to be a good choice for backplane drivers at 160 Mb/s. GTL device from Texas unusable at this data rate, also power dissipation of receiver function becomes too high. The backplane transmission system of the production system should operate from 3.3V, or 2.5V supply (not 5V) to give useful reduction in power consumption. Status of DSS mother and daughter cards - James Edwards ------------------------------------------------------- James showed some diagrams. Lot of concern about the on-going delay in the manufacture. This is due to the very high density, which is being handled by micro-vias, raising the price somewhat. It will take about 5 weeks to have the mother boards. Daughter cards should be here in a few days. It was pointed out that not many tests were possible without the mother board. Could we use Bob's BER tester with some sort of bricolaged interface to the daughter board ? This was considered too restrictive as we won't be able to do all the tests. DAQ Software for LVDS tests - Bill Stokes ----------------------------------------- Some progress has been made in handling histograms. Because DSS specs changed a few further modifications will be necessary. Code written to read out the module worked first time. Some subtle VME to VME problems were sorted out. Hardware Status Summaries ========================= Clock control 'module' - Viraj Perera ------------------------------------- The specifications for this are now on the web. Viraj described the status of the project. Stage-1 of the TTC interface was almost complete. Two CAN bus kits had been connected and were transmitting and receiving messages. ROD - Viraj Perera ------------------ Almost all changes after the review had now been done. Headers, trailers and status registers have now been added. Date format modifications suggested by Norman Gee had been incorporated (see Prototype Draft 6.0). The data format was provisional but expected to converge soon. Some spy event buffer issues to be addressed. Serialising 'ASIC' - Ian Brawn ------------------------------ This has been targeted at a Xilinx Virtex device, and the simulation now works at 178 MHz. The limiting factor is the system clock frequency. Ian presented a scheme for BC de-multiplexing. Paul suggested the addition of a parity bit to check if data had been corrupted. He is also looking at the implications of the costs/implications of the "double logic". May be should also consider a change in name for this 'ASIC' ! CP ASIC plans & specification of the algorithm - Viraj Perera ------------------------------------------------------------ Work is continuing to produce Draft-0 of this. He said that most of the blocks had been specified. Work on the trigger algorithm with Alan was needed. Viraj gave a written description of the algorithms. A description in terms of a VHDL model will be developed by James. Norman would like to convert the VHDL to 'C' and use in the software. Should we be using ASICs or FPGAs ? Viraj will get more information from Virtex and Altera. LVDS daughter cards - Richard Staley ------------------------------------ These are expected to arrive at RAL imminently. Richard can do some crude tests of these without the mother board. G-link daughter cards - Bob Hatley ---------------------------------- The Receiver has gone out for assembly, back within a week. Transmitter still in Drawing Office being laid out. CPM Insertion force onto Backplane Connector - Richard Staley ------------------------------------------------------------- The production CPM will have about 800 pins. Richard had investigated the insertion force that would be required for various connector styles. The METRAL connectors seemed to give about the lowest insertion force of 369 N for ~800 pins. Murrough pointed out that we were critical of JEM modules because their insertion force was estimated to be about 600 N and now we were in the same ball park ! Discussion followed: was a mechanical prototype needed and how would it be constructed ? Did Stockholm make something that was tested ? Norman Gee said that he would ask Sam. Common Merger Module progress - Norman Gee ------------------------------------------ It was agreed that there will be a CMM. The backplane version was preferred and Kithsiri was looking at this (see next report). Other groups would be quite happy to use what we build. We could go out to an engineering specification. Tony suggested that it might be good to build a prototype. Simulation of backplane to CMM - Kithsiri Jayananda --------------------------------------------------- Kithsiri had used Cadence program to study cross-talk. The program was very slow with large swap time delays. Some inconsistencies in the program behaviour were seen. Could the program be trusted ? Kithsiri had calculated the cross-talk for a simple model and compared with the Cadence results: at large line separations the two values were in better agreement but large discrepancies remain at smaller separations. May be help should be sought from Cadence or some newsgroup. Preliminary Design Reviews Status - Tony Gillman ------------------------------------------------ Tony presented the status of all the modules: DSS, PPASIC, ROD prototype module, SASIC, CCM prototype system and CPM prototype module. For reviews that have concluded, summaries should go on the web. Eric commented that the dates of the reports (or version numbers) should be available on the web. Thoughts on prototype system tests - Norman Gee ----------------------------------------------- Norman presented the scenario for DSS based tests this year which would test LVDS & G-link, ROD and ROD+ROIB. He showed a proposed block diagram for system tests. How many modules will be needed ? The modules should be fully instrumented for these tests. Note that the prototypes will have 100 % of the functionality of the final production module. Bunch Crossing identification, calorimeter signals etc. ======================================================= BCID progress and plans for test at Saclay ------------------------------------------ The PSPICE modelling has been modularised. It is now possible to vary properties of towers and thus the parameter space can be expanded. Commenting on the forthcoming Saclay tests Paul said that he was not sure what hardware would be there. Paul, Bill Cleland and Paul Hanke will be there. They hope to produce files which could be useful for future BCID studies. Encoding of serial data for error detection - Paul Bright-Thomas ---------------------------------------------------------------- Paul reported on recent work on optimisation of serial data transmission between PPM and CPM (or JPM). How to maximise error detection and whether to use odd or even parity checking. He used software modelling of data transmission to check which scheme worked best for us. In the TDR we state that a BER requirement of < 10**-9 would satisfy the requirement that Level-1 fake triggers are fewer than 1%. Fancy error correction schemes exist but these impose additional latency costs. Single bit parity check achieves a factor of 2 reduction in fake triggers; more sophisticated block codes over two words give a factor 5+ at cost of 1BC latency. How to read BC Multiplexed data ? - Norman Gee ---------------------------------------------- Norman suggested that we should read 5 time slices in order to observe full pulse shape after the FADC, to check the BCID and BCMUX. This would also help with timing setup and help with data quality monitoring as well with diagnostics. This can be sustained in a scheme where we have a ROD friendly formatting. Software ======== Software Status report - Murrough Landon ---------------------------------------- Diagnostics: DSS software has been there for some time now but will need some updates to respond to latest programming model changes. DAQ: DSS code has now been written and now undergoing series of tests. Software platforms: Linux seems the likely choice. Hardware: What should replace 68K based LynxOS system ? No consensus, not even within the UK ! Other matters: Calibration being looked at; CVS being used and StP CASE tool being evaluated; Readout issues, future of DAQ (evolution towards ATLAS DAQ s/w) and of Diagnostics also being considered. Out of the rut ============== Introduction to the TTC system - Murrough Landon ------------------------------------------------ Murrough gave an overview of the TTC system which is used to distribute the clock and synchronise the signals to all trigger electronics. The PDR for the final version is expected in December 1999. There is a lot of information on the web. Miscellaneous ============= Progress on unified costing: nothing further to report (Norman Gee) Future meetings planning: Eric summarised the forthcoming meetings. Ullrich will give the Level-1 talk at the Atlas week. Joint meeting to be held at RAL 1-3 July at RAL. Level-1 workshop at CERN 14-16 July. LEB workshop late September in Colorado - Viraj will distribute the abstract. Next meeting: Will think about it !