Level-1 UK meeting --- 27th October 1999 (Birmingham) ====================================================== Present: E. Eisenhandler (Chr), J.Garvey, W. Stokes, W. Gibson, R.Staley, A. Watson, I. Brawn, T. Shah, R. Hatley, M. Landon, V. Perera, K. Jayananda, G. Anagnostou, N. Gee, P. Watkins, P. Bright-Thomas(*) 1. Viraj --- DSS tests The DSS motherboard will host two CMC daughter cards, of a number of types, intended to test LVDS, G-link or S-link data transmission, or the ROD prototype. The mother card provides test data from either a DP-RAM or a pseudo-random pattern generator (PRPG), and a comparator to compare received and transmitted data. The Mother card features had been successfully tested with a loop-back connector, showing that the basic data generation and comparator functions were working. With the LVDS cards, there was a problem with initialising the PRPG which generates the pattern against which the received data is judged. A solution was found to initialise the data pattern correctly. In preliminary tests with 8 LVDS channels errors were found in about 50% of channels, independent of which pair of Tx/Rx daughter cards were hosted on a motherboard, with error rates up to several Hz. The G-link daughter cards have all channels working, with no errors seen after two hours of running four channels at the same time. 6 DSS motherboards were manufactured, but there were problems with displacement of the PCB solder mask. Only two of the boards have been assembled, but due to the above problem in the PCB, and difficulties with Xilinx engineering sample CPLDs (for which we weren't sent full specs), resulted in 1 month needed for commissioning the first board (second commissioned in 4 days). Two more boards are to be assembled (urgent). The DSS playback mode must then be tested, followed by tests with the S-link and three kinds of TTC daughter card. The DAQ code will be needed for comprehensive error analysis, and this is still under development. One motherboard and two LVDS Tx/Rx daughter-board pairs have been sent to Birmingham for LVDS testing. The plan is for Birmingham to concentrate on LVDS BER and cable measurements, and for RAL to do various other things such as S-link tests. 2. Viraj --- ROD prototype The ROD PDR spec still needs updating after further comments from reviewers. The attachment of BCID number has been revised, to now be done centrally by the CPM, rather than individually for each Serialiser. The S-link bandwidth is limited to 100 Mbyte/s so zero suppression and compression will be needed on the ROD (note that 5 slices will only be read from the CP serialisers for test purposes). 3. Ian --- Serializer The output skew has been reduced from 2ns to 0.1ns by using output registers but this brings a small latency penalty of 1.8ns. There are some options for making small latency savings, but there is an irreducible latency of 19ns in waiting for the 4th bit of a serial nibble to be transmitted. The predicted minimum overall latency has been reduced from 66ns to 44ns (compare to 1.5 ticks in TDR) but is dependent on relative phases of data and clocks. Self-synchronising logic has been designed to find the optimum timing for input data, but an extra delay pipeline might be needed. The input skew is to be investigated in more detail, after which a full specification will be produced. 4. Viraj --- CP-ASIC/FPGA Draft 1 has been updated following Alan's comments and will shortly be released. The first issue is the way in which BC de-mux and error detection are implemented; if error-checking can be done before BC de-mux data is latched then individual (pairs of) towers can be suppressed, but if not, the whole CP chip hit and RoI output may have to be zeroed. The second issue is the formation of a saturation trigger, which will be set if any of the 70 inputs to a CP chip is saturated. 5. Richard --- CPM The draft CPM spec is still growing, with the PDR scheduled to start in early 2000. A spatial layout of the full module was presented, with a 2-ASIC/FPGA 4*4-window subregion proposed for a CPM prototype, which would be a tight fit on a 6U board. Stockholm want a 6U prototype, but 9U might be more appropriate for backplane tests. There is still an issue over choice of backplane connectors, with Stockholm/Mainz preferring a large number of ground pins, and a connector with a relatively high insertion force. An example of a leverage system for high-insertion force modules used by CDF was said to break after ~10 insertions, and we would clearly need something more robust. 6. Norman --- Merger Module The CMM must be discussed further at Stockholm. This module will force an early decision on a common backplane connector. 7. Kithsiri --- TTC The TTC test set-up at RAL is ok, but there have been some issues with synchronisation. Early experiences have been reported on the TTC questionnaire circulated by Ph. Farthouat. Kithsiri, Murrough and Norman have been designing software objects for the TTC. 8. Murrough --- Cables Mark Hatch of TC has apparently had little contact with the LAr people responsible for cable selection, and it is feared that their cable choice is too stiff for connection at the calorimeter. The holes into USA15 appear to be just adequate for the cable numbers we propose. The LAr cable PRR is scheduled for the 07/12, and Paul Hanke and Bill Cleland will be on the review panel. The 16-pair cables for LAr will be non-optimal for TileCal signals which come in groups of 9 and 6 from the completely separate barrel and extended barrel --- additional pairs are also needed for the back sampling muon trigger signals. The issue of who will take responsibility for designing and constructing the Tilecal receivers is now a pressing one. 9. Eric --- EDMS Eric has had a demo by Nick of the new Engineering Document Management System. It allows multiple versions of a document to be stored (e.g PS, tex, Word, PDF) and also version control. From the ATLAS TC homepage go to docs and log in as "guest" in order to view documents in the system. Eric has an account for submission of new documents to our part of the hierarchy. There is an issue about the ability to link to documents in the store from other web pages, sine the URL's generated are very unwieldy. 10. Paul --- BCID update A long-standing check on long pulses (t_pk up to 80 ns) was presented, showing that 5 coefficients is as good as 8 in the FIR BCID algorithm. However, the fact that coefficients calculated for a 50 ns peaking time seem to deliver better performance that those calculated for the nominal (longer) peaking time suggests that some optimisation of performance can be achieved in the FIR coefficients. Performance of 4-bit and 6-bit FIR filter coefficients was also shown to be equivalent for all pulse lengths. Some preliminary pulse shapes have now been received from Saclay in the form of Excel files and a first comparison of pulse shapes from along the LAr electronics chain, and against the PSPICE model was made. The cable integration effects seem to be relatively small (from comparing 50m and 70m cable lengths), but the real pulses have a much quicker take-off than the PSPICE predictions. A list of information required for calibrating the BCID algorithms was presented in response to an enquiry from Tara, who is looking into calibration issues. The latency and phase of the pulses must be determined, together with pulse shape for FIR coefficients, noise for LUT thresholds, ET scale, saturation level, evolution of pulse shape when saturated, and possibly crosstalk. Work should begin on specifying the algorithm that would enable these parameters to be determined, bearing in mind that complex interaction with the calorimeters' calibration systems will be required. 11. Paul --- TileCal issues PBT and EE attended the TileCal adder review in April; results from testbeam with prototype adder board were presented in September ATLAS week (http://www.lps.ufrj.br/cern/atlwset99.pdf). Our major point from the review was that the gain scale of the adders should be changed in order to avoid "premature saturation" of the towers for 1.4