ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 07 February 2000

Minutes

Present: Tony Gillman, Bob Hatley, Viraj Perera, Richard Staley

1. LVDS (and other transmission) issues
Richard will aim to submit his ATLAS Note on the results of his CMOS backplane 
transmission studies before the next meeting on 15th February.
The re-designed LVDS Rx daughter-cards are now out for manufacture (2 off), and will 
be available for test by the end of February. Richard will repeat some of the BER 
measurements with these new cards, also using the TTC system for the first time to 
assess the effect of clock jitter. The LVDS Tx daughter-card will be re-designed (better 
decoupling, etc.), and will also incorporate a high-stability ECL PLL from SYNERGY 
(10 psec rms jitter), which will be capable of being bypassed to assess its effectiveness.
The suspected TTC jitter problem has still to be confirmed, but the solution of adding 
an extra PLL to each PPM would in principle remove its effect on the LVDS serialisers.
Bob reported on the latest results from his tests of G-link data transmission. He is able 
to transmit single-ended data at 960 Mbaud over a halogen-free coaxial link of total 
length 19m (consisting of a non-ideal bricollage of several inter-connected cable 
sections!), with a BER of <3.10-12, which is very encouraging. As the G-links will now 
only be used for transporting data to the RODs (and not for PPMs ? processors) it is at 
present unclear what BER is acceptable, so a study will be undertaken. Bob will repeat 
the tests using four links between a pair of DSS modules in two different crates, driven 
from the TTC system to assess the effect of any jitter. The cable lengths will be fixed 
between 15m and 20m, depending on the proposed final location of the ROD crates. 
The tests will be done using a "burst" mode of operation, triggered by a Level-1 Accept 
signal at up to 100 kHz, for which new DSS firmware will be needed - Viraj will look 
into this.

2. CPM prototype status
Richard has been making progress on the specifications document, but the area of read-
out control needs further clarification with Viraj. The backplane connector type is now 
defined as Berg Metral, with the screened version available as a "customer special" on a 
12-week delivery time. The pin allocation with the connector is also now broadly 
defined, and agreed with the JEP system designers. One remaining issue is the exact 
specification of the VME bus, which Norman is looking into.
The date for the Preliminary Design Review for this module was proposed as Friday 17th 
March 2000, with the documentation to be made available by about 6th March. Tony will 
suggest the names of four reviewers, and a location for the review, before next week’s 
meeting.

3. DSS status
Viraj summarised the current status of the DSS modules. All four are fully working, but 
two modules still have the engineering sample versions of the VME CPLDs, which 
require an awkward post-power-up procedure. A software patch to overcome this 
problem has not been successful, but has managed to speed-up the procedure. 
Unfortunately, replacement of these devices would be very hazardous, with the risk of 
seriously damaging the on-board solder pads and surrounding surface-mount 
components. It was therefore decided to delay this work until more DSS modules 
existed, and a further six boards will now be ordered (components were originally 
purchased for a total of ten modules). Viraj explained that we will hopefully get four 
boards at no cost, as the pcb manufacturer had made errors on the original four boards - 
this is currently being negotiated. If modified artwork related to the S-link design is 
requested, there may be some additional NRE costs.
The A24/A32 problem has now been resolved, due to Bruce’s perseverance, and was 
shown to be software-related. It was suggested that documentation on the use of the 
LynxOS system be provided.
Viraj agreed to add the Test Plan to the DSS specifications document, and to ensure that 
it includes full details of the board jumpers and base address settings.

4. ROD prototype status
Viraj reported that Kevin has been working on the I/O pin-definition of the FPGAs. 
Agreement has been reached for the ID System Design Group to purchase the PCI 
"core" design (~£5K), and a free evaluation kit for development has already been 
ordered. All significant components have also been ordered. Good progress has been 
maintained on all aspects of the design, and the target date of end-March for submission 
to the Drawing-Office should be met. The board will contain a total of three BGA 
packages, one of them a "fine-pitch" device (1mm, c.f. 1.27mm for normal BGAs). 
Efficient testability will therefore demand the extensive use of boundary-scan 
techniques, so a boundary-scan kit will be ordered by the System Design Group 
(~£20K).

5. Reviews
Tony reported that the PDRs for the PPr MCM and CP ASIC/FPGA were successfully 
concluded at RAL in late-January. The new format (e-mail plus a one-day discussion) 
was generally considered an improvement on the previous structure, and will be adopted 
for all future reviews.
He added that the summaries of the two reviews were still being drafted, but that they 
would be completed this week and sent to Ullrich and Viraj before being posted on the 
Web.

6. CP ASIC/FPGA status
Viraj reported that James will begin serious design work on this chip in April, as soon 
as the ROD design passes to the Drawing Office for layout. The front-end de-serialising 
and BC-de-multiplexing design work that Ian is currently doing will be directly 
applicable to the CP chip.
Interim estimates of the total gate-count of the device will be made at periodic intervals 
in order to assess the likelihood of an FPGA implementation - or the need for an ASIC.
Recent progress still indicates that the target date of end-June to complete the design is 
realistic.
Paul B-T will supply a slightly modified version of his proposed local terminology for 
the cells, primitives and thresholds in the chip, to be included in the specifications 
document.

7. TCM prototype status
Bob circulated the latest version of the specifications for the TCM and for the TTCdec 
card. It was agreed that comments from everyone would be discussed at the next 
meeting on 15th February, after which the document would be sent to our non-UK 
colleagues.
The issue of impedance-matching of the TCM and (as yet unknown) backplane TTC 
pcb traces was discussed, but it was decided that the TCM tracks could be kept short 
enough to disregard their impedance.
Tony agreed to confirm the availability of the ten prototype TTCrx chips from CERN, 
and to order them as soon as possible.

8. Alternative link architectures
There was some discussion about the Virtex-E + Paroli (optical) architecture described 
by Uli, but no conclusions were reached. Many questions are raised by the scheme, and 
it was felt that it the necessary tests would involve a significant delay to the current 
prototyping programme. Nevertheless, the implications should be discussed at the next 
"brainstorming" meeting on 3rd March.

9. Any Other Business
There was none. 


Next meeting - Tuesday 15th February at 13.30 in CR11, R3 at RAL.


Tony Gillman