ATLAS Level-1 Calorimeter Trigger Hardware Progress Meeting - 07 March 2000 Minutes Present: Ian Brawn, Paul Bright-Thomas, Bruce Barnett, Norman Gee, Tony Gillman, Bob Hatley, Richard Staley 1. Heidelberg “brainstorming” meeting Norman and Tony summarised the most important conclusions from this very useful meeting, attended by Paul Hanke, Ullrich, Juergen, Uli, Sam, Eric, Norman, Tony and Viraj, the agenda of which was as follows: a) LVDS links TTCrx timing jitter - solutions? Plans for further tests in Birmingham Tony Mainz tests Uli Heidelberg tests Paul (Discussion) It was generally agreed that the simple addition of a low-jitter PLL on each PreProcessor and Processor module could reduce the large jitter seen on the TTCrx clocks, and enable safe LVDS Tx operation. The Mainz group had tested (with very low BERs) a 15m section of single-channel low-smoke, zero-halogen flat ribbon cable from AMP (TYCO) which looked very promising. Its adoption would imply changes to the current backplane pin-out proposals, but it would have several advantages over the 4-channel assemblies tested to date. There are questions of availability and cost. For LVDS fan-out, the Heidelberg group are designing a four-channel dual fan-out buffer ASIC, and Richard Staley has also identified a promising commercial chip from TI (SN65LVDS104). b) Other items of common interest: PPM “Module 0” specifications - status Paul Common Merger module specifications - status Norman Use of TTCdec cards and TCMs by all 3 sub-systems? Tony (Discussion) Paul described the current ideas for the PPM Module 0. After allowing for the VME space (120 mm) and the Pipeline Bus space (60 mm) he noted that there would be a “generous” 160 mm of backplane height available for the necessary 62 LVDS output signals to the Processor crates (c.f. 80 and 96 LVDS inputs needed on the CP and JEP system backplane connectors). A space-model of the backplane connector/cables matrix will be very useful for anticipating potential access/extraction problems. A connector extraction tool may be required. For the Common Merger module, Norman described how the input bandwidth via the backplane connector could be increased by providing one of the output blocks with bi- directional I/O capability when used for energy summation. Paul Hanke will make the necessary changes to the PPM and associated backplane to allow full use of both the TTCdec and TCM. c) ROD prototypes (for information only): PPr ROD status Paul CP/JEP ROD status Viraj Paul Hanke described how the PreProcessor ROD prototype would consist of a CMC daughter-card located on the Heidelberg VME test module, connected to the PPM Pipeline Bus via a cable link. The final PP ROD design is 1-2 years away. d) Issues to be resolved urgently (* may need more work/time): Prototype CP/JEP backplanes to “Module 0” specification? Prototype module/crate format – 6U or 9U? Backplane connectors and pin-out? VME specification? * LVDS link cables? * It was finally agreed that the JEM and associated backplane should be designed in a 9U format. Uli had obtained some estimates for the manufacturing costs of 9U pcbs which appeared very high, so it was agreed to design the JEMs to the full “Module 0” specification, rather than design a prototype module with reduced channel-count. It was accepted that specifying and designing such a module would take longer. More information would be obtained from pcb manufacturers in the UK to try to understand what drives up the costs. Uli proposed a major simplification to the two Processor systems - use identical backplane connector pin-outs. Assuming it is possible to design a backplane connector pin-out to provide enough I/O for the JEMs (88 LVDS input signals + 330 inter-module fanout signals), then the CPMs would need only a sub-set (80 LVDS input signals + 320 inter-module fanout signals). All other signals (VME, TTC, CAN- bus, etc.) are needed equally for both Processor systems. It was agreed that this would be an important goal, so Sam and Richard will work towards a single pin-out definition. No final conclusions were reached regarding the exact VME specification, but a VME “Task Force” was established, with Norman and Sam defining the minimal set of VME signals needed by all sub-systems, and Viraj and Richard deciding whether 3.3V VME operation (to minimise backplane noise) was viable. Sam would be responsible for producing a recommendation by the time of the Mainz meeting. If the AMP cable assemblies noted earlier (Part no. 621408-6) prove satisfactory on availability/price grounds (further quotes to be sought in Germany, Sweden and the UK) then these would form the preferred interconnection medium, together with the corresponding AMP Z-Pack backplane connectors. The question of increased insertion forces c.f. the BERG connectors was again raised, but not resolved. e) Alternative link architectures: “Front-end” links - Virtex-E + Paroli proposal Uli Other fall-back options for “front-end” links? “Back-end” links - G-link or Channel-link? Viraj (Discussion) Uli presented a foil indicating that a Virtex-E FPGA driving serial LVDS bitstreams into Paroli optical transmitters would demand even better clock jitter performance than the NS LVDS Tx part. At this late stage this architecture was therefore not such an attractive option as at first sight, especially as a major demonstration programme would be essential. Also, the PPr MCM would need tracking and component placement modifications to feed the 30-bit parallel data out on an additional connector, so on balance it was decided not to pursue this proposal at present. However, it would still be possible to reconsider it later (before volume PPr MCM manufacture) if there were an insoluble fatal problem with the current LVDS approach. f) Future target dates: PDRs - CPM, JEM and CMM prototypes? Milestones? The awaiting airport taxi (and the general fatigue level in the room) caused this item to be postponed until the Mainz meeting. 2. Birmingham hardware - LVDS, CPM prototype, etc. Richard reported that with the LVDS link test system now set up and working in the newly-occupied Trigger Laboratory he will measure the PLL clock jitter on the DSS module. The new LVDS Sink daughter-cards are expected to be back at RAL by 10th March. Richard will draft the specifications for the new LVDS Source daughter-card before the next Hardware meeting. The design will include an additional low-jitter PLL, LVDS fan-out using the TI SN65LVDS104 chip and an appropriate cable pre- compensation network. If the schematics can be drawn quickly, the RAL Drawing Office currently has spare capacity to carry out the layout. He agrees that the CPM prototype module will be designed to a “Module 0” specification, with a full complement of channels. As he will therefore now require a little more time to modify and complete the specifications the PDR planned for April 10th will be postponed until May, the new date to be decided at the Mainz meeting. Note that the prototype level-1 trigger slice will now consist of “Module 0” specification PPMs, CPMs and JEMs and CPM/JEM backplanes (but still only prototype RODs and TCMs). Finally, Richard noted that the ATLAS Note on backplane CMOS transmission studies had progressed to a pdf version, and he will attempt to submit it to the CERN EDM system before the next Hardware meeting. 3. Final CPM -> ROD G-link tests Following on from his work on PPM -> CPM link BERs, Paul offered to consider how we might determine the maximum permissible BERs for the CPM/JEM -> ROD links carrying RoI data to the level-2 trigger. At present, we have no information at all on the data integrity required of these links, or what the impact of different error conditions might be on the level-2 trigger. The planned burst-mode tests on the G-link Source-Sink daughter-card system will be carried out when the 25m cable assemblies are available. Bill believes that the DAQ code already supports the necessary burst-mode operation. 4. ROD prototype design status Ian reported that James and Kevin are making good progress with the firmware and schematics. They are still on target for submitting the design to the Drawing Office for layout at the end of March. 5. Serialiser and CP FPGA status Ian reported that the Serialiser simulations were now complete, showing operation at up to 176 MHz with the pin-out chosen automatically by the Xilinx software. Any re- definition of pin-out would require re-simulation. The latency is currently 2 bunch- crossings. Information about the bit allocation in the PreProcessor LVDS data words is now needed from our Heidelberg colleagues. For the CP ASIC/FPGA, Ian noted that the front-end de-serialisation function has already been coded into firmware, and the necessary simulations carried out. Viraj has produced a description and specification of the proposed generic test module for the Serialiser and CP ASIC/FPGA, which Ian summarised for us. Additional effort is planned for the design, as it will be shared with CMS. Some questions were raised regarding the capability of this module to test fully all features of the two chips, which will need further discussion at the next Hardware meeting once we have read Viraj’s write-up. 6. Post-Heidelberg CMM status Norman showed the latest block diagram of this module (as discussed at the Heidelberg “brainstorming” meeting), and noted that the draft specifications were still in progress. He will have a final draft available for presentation at the Mainz meeting. 7. Any other business. There was none. Next meeting - Tuesday 28th March at 11.00 in CR01, R1 at RAL. Refreshments will be provided. Tony Gillman