Dear colleagues, Here is my now-traditional summary of the points that I think stood out at the Heidelberg meeting, in a more readable form than the hand- written transparencies that I showed. As always, these are my own personal views and are not aimed to be a comprehensive summary of all that was presented and discussed. I do apologise in advance for anything important that I have missed, and if you think anything is mistaken or objectionable please let me know and I will correct it. The categories are as follows: + is a positive, or mainly positive, development, or something that has been sorted out, or simply good progress. - is a negative development, or something that needs to be sorted out that may cause problems, or an item where work seems to have stopped - no criticism of people involved is (necessarily) implied. * flags work or a decision that is needed. ! is a point that is controversial that must be discussed further. I do not mention names since it would be very difficult to be fair to everyone who has done all the work listed - I assume people will know who they are. Once again there are only a few negative points, but there are disturbing trends such as 'coherent' slippage in meeting deadlines. There is a very tight schedule to get to the slice tests, and we cannot afford to be complacent! cheers, Eric (7/11/00) ----------------------------------------------------------------------- Physics simulation + Continuing development of ATLFAST-L1 and work on jet triggers. * Think about how to put this into the new s/w framework ATHENA. + Serious work is finally getting under way on new ATHENA version of ATRIG; we are involved. - Progress on ATHENA and how to use it seems disappointingly slow (this is not a trigger internal issue!). * Do we need to put more effort into this area? Calorimeter signals + LAr trigger cable passed its PRR and looks good. * Need to tie to the main order our short cables from receivers to Preprocessor Modules, as well as the long TileCal cables. - TileCal seems to have forgotten our groupings of 6 pairs (barrel) and 9 pairs (extended barrel). * Need new contact person for TileCal. + Tilecal signals looked at in test beam. It seems as if we can use the front-end of LAr receiver for TileCal. * Must find effort to build TileCal receivers. (New group?) Preprocessor + Much thorough work has been done to simulate and understand the ASIC since its FDR. + The BCID decision logic has been improved. + Work on the MCM continues, and there are nice plans for testing the prototype (such as the use of video RAM for analogue testing). + There are good test results on the prototype ROD. * The Preprocessor ROD must be added to the review process. To ease the load we will try grouping it with PreProcessor Module reviews. + Work is continuing on the design of the Preprocessor Module. - Delays in finalising the ASIC (to be sure it is right on the first round) have held up both the MCM and the Preprocessor Module. + 'Homebrew' VME PC is nearly working. Less controversy on this now. * Documentation on the ASIC and MCM needs updating. Serial transmission + New faster LVDS receivers have transformed the situation from 'acceptable' to excellent', they are much more tolerant. + Bit-error rate now down to around 10^-14 (and no errors). * Some questions about footprint and die availability of the new transmit chip are not yet answered. + Rack layout has been revisited. Some new ideas were floated, and a nice table giving ranges of estimates of cable length was shown. + It looks as if LVDS link cables might be well under 10 m in length. * Must re-check positions of holes in the shielding wall, etc. Cluster Processor + The CP chip is now quite advanced, and is being checked in simulation with test vectors. + CP chip latency appears to be 6 +/- 1 b.c. 6 b.c. was in the TDR. + The cost of Virtex-E chips has decreased. + Conclude that we will adopt the FPGA solution instead of an ASIC. + Generic Test Module will be used to test both the Serialiser and the CP chip. * More test vectors are needed. + CP Module passed its PDR, and the specification has been updated. + Detailed internal nomenclature has been worked out. The JEM should use the same principles. - Design of the CP Module is running slower than planned. Jet/Energy-sum Processor + The design has been re-organised to optimise handling of the FCAL. + The number of FPGA stages has been reduced, mainly for latency reasons and FCAL handling. ! The prototype will not be to module-0 standard for the slice tests, but the differences are not huge. Why isn't the prototype 40 cm deep, and so why not 'nearly module-0' like other modules? + Nice work has been done on improving the energy-sum chain. - Design of the JEM is running slower than planned. Common modules + The specification of the Common Merger Module is progressing. + Improvements have been made to its energy-sum logic. - Work on the CMM is running slower than planned. + The CP/JEP ROD prototype is being tested, so far quite smoothly. + The Timing Control Module design is progressing well. + Some ideas on the adapter link card for the TCM, and on personality cards for CPUs in VME were shown - these allow the same TCMs and CPUs to be used in both Preprocessor (standard VME) and CP/JEP. * We should think about how to handle CPUs that are double-width. * The CPU personality card for the CP and JEP will be needed for the slice tests. CP/JEP backplane + The design is nearly final, with the PDR on 20 November. + Work on the mechanical demonstrator has only just started, later than planned, but things look very promising. + 'Live' insertion is 'dead'. DCS * Must decide on usage or not of ELMB in for these prototypes. We need to trade off money vs. board space vs. shortage of effort, and also to define what we really want to do on individual modules. Timescale - It was a 'long summer' in all areas ... but + PDRs are about to resume in a big way. * The Common Merger Module is the critical path item en route to the slice tests. + A proposal for rationalising and improving our long-term milestones was presented and will be decided on soon, after reactions gathered. Online software + Improvements have been made to HDMC, and Qt Designer looks nice. + Work on DAQ software is progressing. - But ATLAS DAQ group is dragging its heels on monitoring that needs to combine data from different RODs. ! The strengths of HDMC are not always what is needed for DAQ, as opposed to diagnostic, software. We must discuss how to progress. + The ATLAS DAQ group has made good progress on online software and detector DAQ. - But some essentials are still missing. - A huge amount of software is needed for slice tests, and the effort available is not sufficient. ! Should we set software milestones, and what should they be? Tests and integration * ROD to RoI-builder tests, and ROD to ROS (ex-ROB) tests, are planned for February/March 2001, with minimal hardware and effort. * Integration tests with DAQ/HLT to start around mid-2002, only after the end of the main slice tests. * Define 'end of slice tests' by setting minimum requirements to meet. * Do not forget integration tests with LAr and TileCal - signal chain including receivers, calibration, etc. Management Committee + New costing was completed and spend profiles submitted. The costing spreadsheet is an excellent framework for future requests and changes. General comment + Comparison with the previous 'highlights' summary shows that a lot of issues have been resolved, and a great deal of progress has been made.