ATLAS-UK Level-1 Calorimeter Trigger Meeting
Monday 18th September 2000 - RAL
Present:
Bruce Barnett,
Ian Brawn,
Paul Bright-Thomas,
James Edwards,
Eric Eisenhandler (chair),
John Garvey,
Norman Gee,
Reg Gibson,
Bob Hatley,
Murrough Landon,
Ed Moyse,
Viraj Perera,
Azmat Shah,
Bill Stokes,
Scott Talbot (minutes),
Pete Watkins
Agenda
Minutes of previous meeting
Data transmission
LVDS: new results and plans......................Richard 10'
Hardware status summaries
Generic test module................................Viraj 10'
Serialiser...........................................Ian 10'
CP "chip"..........................................Viraj 10'
CP Module........................................Richard 10'
ROD prototype......................................James 10'
Timing Control Module................................Bob 10'
Common Merger Module..............................Norman 10'
Backplane, connectors and cables.................Richard 10'
Imminent review schedule............................Eric 5'
Online software
Brief summary of software meeting and status....Murrough 10'
Other items
Costing and spend profile.........................Norman 10'
Trigger/DAQ reorganisation status...................Eric 5'
Coming meetings and workshops.......................Eric 10'
Any other business
Dates of next meetings
Data Transmission
As Richard was absent Eric gave the details he knew of the status of
the LVDS tests and Paul added more information when he arrived.
Richard has been testing the new faster LVDS chipset and lots of problems
disappear. The tests have been very successful and given no errors on
overnight tests on cables up to 20 m long. The clock jitter problem has
disappeared.
There are various transmission and receiver chipsets available
covering the frequency ranges 12 - 40 MHz and 40 - 66 MHz. Richard
will not test the different combinations.
Hardware status summaries
The module has been in the drawing office for nearly four weeks and
the placements of components is almost finished. The routing will then
be done. The module should leave the drawing office around the end of
the month and be manufactured during October.
Viraj hopes to have a module for testing in November.
Ian has updated the design to match the current specifications and the
tests at 160 MHz have been successful.
He is now checking the pinout and putting all the 160 MHz output pins
into three of the Xillinx pin banks so that the voltage level for this
section can be independent of the rest of the chip.
Some work is needed with Richard to finalise the design then the
serialiser will be finished.
The current design uses the smallest available chip. The next larger
chip, which has the same footprint, will give more leeway and so needs
to be costed.
Tests on the updated design above 160MHz have not been done, but the
previous was successfully tested above 170 MHz and so Ian does not
think there will be any problems.
James is designing the algorithm block and has been given the
serialiser/de-serialiser blocks from Ian.
Test vectors from Alan will be needed very soon and James will contact
him to let him know what he needs.
There is some inconsistency in the specifications about whether the
thresholds of the left and right side of the RoI block are
independent. Unless requested otherwise, the chip will be designed
assuming that they are not independent.
It is hoped the latency will be known by the Joint meeting in
November.
Richard is still working on the specifications. There is some ongoing
discussion about how the registers should be ordered and the
programming model may need to be revisited to reduce the complexity of
software programming.
The post PDR documentation is in limited circulation. There are still
some items which need to be discussed. Richard is starting the
design the module. It should take about 1 month to finish the
schematics.
There is some possibility of using flash memory instead of
EEPROMs. These are larger and cheaper but are slower to load, although
with some thought about how the loading is performed this may be
overcome.
The design software package has been ordered for Birmingham.
The two manufactured RODs have had boundary scan tests performed. One
board is clear and the other has no major problems.
The RODs are now been tested in the crate and the VME registers can be
read.
It is hoped the ROD will be available for full testing within a couple
of weeks.
The basic system and design of the timing, control and VME display
sections of the module have been worked out. There is some more design
to be done.
Four prototype modules will be made for the next tests.
More thought is needed about the "personality" board. This surrounds
the standard 6U board with a 9U extender, allows the crate number to
be set, connects the CPU to the backplane and does anything else we
decide.
The specs were passed to Ian before the summer and the suggestions are
being worked into the draft.
The latency needs to be calculated and there was some worries that the
single input device may not work as the different systems give
different style inputs and hence will have different parity bits.
Uli has questioned the number of bits used for system-level energy
merging. The draft specs are available.
Preliminary backplane specs from Sam were made available a while
ago, but not all interested people were informed.
The sequence of the high-level future reviews is now very different
to the milestones given in the TDR.
The CPM PDR is still been worked on, but should not be too far away.
The scheduled dates for the CP/JEP backplane and CMM prototype PDRs
were September and the JEM and PPr module prototype PDRs were October,
but these dates have slipped. They cannot be allowed to slip too much
further otherwise it will interfere with next years system tests.
The PPrASIC FDR took place in June, but the updated specs are
still outstanding.
The PPr MCM FDR is scheduled for December.
The stage 1 system tests are scheduled for May, and the system slice
tests starting in July. These tests should be started before the summer
holidays otherwise the delay will be significant.
Online Software
There had been a software meeting in the morning.
The software status is not as advanced as hoped and effort is been
focused on the ROD tests.
Bruce is working on the DAQ/HDMC, Scott on the event dump, Bill on the test
vectors and Murrough on HDMC.
There is still a lot to do.
The software probably won't be ready when the ROD arrives and various
meetings mean it is unlikely to be ready before the end of October.
Other items
CERN had asked for a CORE spend profile, and so Norman has done
a full re-costing for everything in a unified format.
A spreadsheet is available which knows about every item, dates,
etc. and can provide the information about CORE, non-CORE, total
spend, etc. It has all been checked and agreed, and the profile
has now been submitted to CERN.
Andy Lankford sent out a long email when he was elected. He will only
be the coordinator for two years due to teaching commitments.
2 - 6 October ....... ATLAS plenary at CERN
inc. ROD and DCS workshops, TDAQ plenary session
2 - 4 November ...... Joint meeting at Heidelberg
13 - 17 November ...... TDAQ week at CERN
Winter/Spring 2001 .... TDAQ workshop outside CERN
19 - 23 February ...... ATLAS plenary at CERN
March 2001 ............ Joint Meeting at Birmingham (or RAL)
********** Next UK meeting **********
Friday 20th October
Birmingham