ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting – 10th April 2001

Minutes

Present: Ian Brawn, Eric Eisenhandler, Tony Gillman, Bob Hatley, Gilles Mahout, 
Viraj Perera, Richard Staley

1. CP FPGA status
There was no further progress to report on this item, as it awaits James Edwards’ 
return from ROD-land.

2. Generic Test Module
Viraj reported that the re-work from SDI had not been successful, and the original 
problem remains. The company has suggested that two or three re-works may be 
required, and we await their report. We have asked that the replaced chips be removed 
so that we can examine the re-worked pads on the bare board. RAL Purchasing 
Department has been informed.

3. TCM and Adapter Link Card
Bob reported that the layout of the TCM and Adapter Link Card (ALC) designs are 
both well-advanced. Dan Beckett is routing the controlled-z traces manually, with the 
Autorouter being used for all other traces. Bob Thompson has been sent a Bill of 
Materials for procurement.

4. CPU Personality Card
Following the meeting on Thursday 29th March, when the overall requirements of the 
CPU Personality Card (CPC) were discussed, Bob reported that the schematics are 
now complete, and should be informally reviewed. Details of the necessary 
mechanical support structure for the CPU are now being addressed, and a slot has 
been booked in the Drawing Office.

5. Crates, power supplies, Backplane connectors, …
There is a problem with getting hold of the Backplane connector guide-pins – AMP is 
the only supplier and Sam Silverstein can obtain only 10 samples. We will try to get a 
further 10 samples in the UK (20 needed in total).
We would like to see the dimensioned Backplane engineering drawings to ensure that 
the CPC layout has the J2 connector in exactly the correct position – Tony will ask 
Sam to supply a copy.
Bob has ordered 5 sets of 5V/3.3V power supplies (3 weeks delivery) and all the 
necessary accessories to make up 5 complete power supply systems. He will construct 
the first system, and one of the Birmingham University technicians (Roger) will be 
asked to construct the other four.
Bob has discovered that 400mm-deep cooling fan-trays are available from 
Radiospares if necessary, at ~£180 each.

6. CPM
Richard presented his current set of 40 sheets of schematics, and is hopeful that an 
informal review can take place in early-May, and that the layout can start shortly 
afterwards. The unfinished areas include:
? TTCrx interface (still to be packaged)
? Readout controller (requires RAL FPGA code)
? Hit summing code complete (still to be packaged)
A Bill of Materials hopefully will be sent to Bob Thompson within the next 2 weeks.

7. CMM
Ian reported that re-labelling the Xilinx device took Panagiotis 5 days, and this must 
now be re-done as the decision was taken after the last meeting to re-package the 
functions into 2 devices.
It is hoped to hold an informal schematics review before the end of April.
There may be a potential clash with the CMM, CPM and CPC Drawing Office 
schedules clashing, as only Dan Beckett is available for this work. Tony will check 
the situation with Chris Day.

8. AOB
a)	Eric reported that Dave Mills is now sending CAN-bus data frames, but only 
about 10% are actually received and are as yet of unknown quality.
b)	Eric reminded people that Abstract/Summary deadlines for the LEB and IEEE 
conferences are imminent. There are three potential papers:
? The use of FPGAs to provide multiple functions in the CMM - Eric and Norman 
to draft
? The ROD prototype development programme and test results – Viraj to draft
? The Pre-Processor MCM development programme – Heidelberg group to draft
c)	At the previous meeting it was suggested that we order all the G-link chipsets 
as soon as possible, but estimates of the exact numbers led to various questions of 
modularity in the RODs, so it was proposed to discuss this issue further at the next 
Group Meeting.
d)	Viraj reported that Adam Davis (Kevin Hatton’s successor) will design the 
LVDS parallel data I/O CMC board for the DSS module, for use with the CMM. 
Essentially, it will consist of a single large FPGA configured to provide 32 pairs of 
LVDS I/O pins, or 64 single-ended CMOS I/O pins, with a 68-way SCSI connector 
for cable connections.

Next meeting - Tuesday 24th April at 14.00 in CR01, R1 at RAL. Refreshments will 
be provided.