ATLAS Level-1 Calorimeter Trigger Hardware Progress Meeting – 11th July 2001 Minutes Present: Ian Brawn, Eric Eisenhandler, Norman Gee, Tony Gillman, Bob Hatley, Gilles Mahout, Richard Staley 1. CP FPGA Ian reported that James had discovered a bug in the latest release of the Xilinx software, which is now under investigation by Xilinx. He cannot target devices until this problem is solved, but if this does not happen soon it may be necessary to revert to a device where the pin-out may be slightly different from that currently assumed for the CPM. This would involve some (minor) changes to the CPM schematics – preferably before the job goes to the Drawing Office for layout. James will summarise the situation at next week’s group meeting, and also explain the problems he has been finding with timing simulations, where a move to using 2-phase (rather than 4-phase) clocks may help. In addition, the top row/bottom row algorithm confusion still needs to be corrected, but this should not take him long. 2. Generic Test module Ian reported that there had been no further progress with using the original faulty module as a test-bed for BGA re-working trials at Cemgraft. The two new boards are now fully-assembled and awaiting JTAG testing. 3. TCM and Adapter Link Card Bob summarised the current status. One TCM/ALC is fully-assembled and under test in the old 9U demonstrator crate, two further boards are partly-assembled and there are a further four bare pcbs. All the front-panels are currently being made. On the first module being tested, all the fanned-out TTC signals are present - front- panel and backplane variants. To test the VME functionality, including the front-panel displays, a VME -> VME-- adapter cable will be needed. To test the CAN functionality, software from Dave Mills will be needed. For documentation, the board layouts (floor-plans) should be available as Web- accessible .ps or .pdf files. 4. VME Mount Module (VMM) Bob reported that the pcbs are due back from the manufacturers on 2nd August, and will then be assembled. Components and pcbs for a total of six modules have been ordered. 5. Crate power supplies Bob reported that assembly of the first unit is almost complete, and should be ready before the end of July, when it will be sent to Birmingham University to act as a model for a further three units to be assembled. 6. TTC decoder cards (TTCdecs) Bob reported that a further seven cards had been assembled, but not yet tested. We now have a total of ten TTCdecs, with a further four CERN Test Cards for use on the DSS modules. 7. ROD tests – current status Norman reported that several aspects of the RoI and Slice functionality still remain to be tested, but there was no further progress to report. It was pointed out that the JEM might be the first real “customer” to source data to the ROD, but that as yet there existed no FPGA firmware to support this. 8. CPM Richard reported that there were now 47 pages of schematics on the Web, and that he had already had several useful comments and corrections from James, and comments from Murrough regarding the programming model. He noted that there were eight unused spare pins on the Serialiser FPGA, and 16 unused spare pins on the CP FPGA – should they be interconnected, or brought out to test-points, or … ? He plans to use spare capacity in the Serialiser FPGA configuration memory (8 Mbyte) to store the FPGA configuration files for the Readout Controller and Hit Sum logic. This is efficient, and also has the advantage of allowing all FPGAs to be configured from VME. The internal schematics review should be completed by the end of July, so that the job can move to the Drawing Office, who will first have to add component designators. In Richard’s absence, the completed net-list will then be checked by Gilles, who has written some appropriate Design Rule Check software (not available in the Cadence design suite). Richard will supply Bob Thompson with the Bill of Materials for ordering as soon as possible. Norman will create a new Cost Centre for these orders, and for the FPGAs ordered via ID. 9. CMM Ian and Norman reported that the design was ready for submission to the Drawing Office for layout once the output connector type had been selected. As information on the CERN-proposed SCSI-4 connector-cable assemblies was still incomplete (impedances, halogen-free material, … ) the current proposal was that we should revert to using SCSI-3 connectors, at least for the prototype CMM. This was generally approved, and so the design will move to the Drawing Office next week. 10. Surface-mount assembly and re-work options Tony described the visit that Eric, Gilles, Richard and he had made to Cemgraft in the morning. They had been favourably impressed with the facilities and experience demonstrated by the company, which they believed would be responsive to our potential needs for BGA re-work. They had some concerns regarding the company’s ability to service 9U boards, so Richard suggested asking them to re-work some chips from one of the old demonstrator CPMs as a trial. 11. FPGA firmware management Following Eric’s suggestion, there was some discussion about how best the ID engineers should review, document and maintain the growing volume of FPGA code. Ian commented that it was perceived as a major issue in the ID System Design group generally, but that as yet no significant work had been done to address it. 12. AOB There was none. Next meeting - Tuesday 24th July at 14.00 in CR01, R1 at RAL. Refreshments will be provided.