ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting – 27th March 2001

Minutes

Present: Bruce Barnett, Ian Brawn, Eric Eisenhandler, Norman Gee, Tony Gillman, 
Bob Hatley, Gilles Mahout, Viraj Perera

1. ROD testing
Bruce and Norman reported on the excellent progress which has been made with the 
extensive tests of the DSS-ROD system in Lab 12, now controlled by the new VME 
CPU from Concurrent Technologies. Long overnight “soak tests” have been carried 
out, running error-free with a level-1 ACCEPT rate of up to 100 kHz.
Two problems remain. The behaviour of the BUSY signal appears anomalous and is 
being investigated by James. There is a potentially serious effect related to any 
momentary disturbance of the TTC signal, when the TTCrx receiver chips appear to 
lock up and can only be restored by a power down-up sequence. This will be 
investigated further.

2. CP FPGA status
Viraj and Ian reported that James has a test bench working and is awaiting yet more 
test vectors from Alan.

3. Generic Test Module
Viraj reported that one of the two modules has now been supplied to the Bristol CMS 
group, with the other still with STI for re-working. There has been no further news of 
its prospects, and it is still possible that a new board assembly will eventually be 
needed.

4. TCM and Adapter Link Card
Bob reported that Dan Beckett in the Drawing Office is working on both the TCM and 
ALC in parallel, and making good progress. Sam Silverstein has offered to order the 
“difficult” backplane connector parts (the ones with very large minimum order 
quantities from AMP in the UK) from EPT or other sources in Sweden. Bob pointed 
out that the pcb mounting holes may differ between manufacturers.

5. CPU Personality Card
Bob reported that he has now started the design of the CPC, but he is concerned that 
there its specifications are still rather vague. For example, how should the crate and 
processor reset signals be handled? It was proposed to hold a brief meeting on 
Thursday 29th March at 14:00 to informally discuss the overall requirements.
This card could become a critical-path item.

6. CPM
Gilles presented the status of the work that he and Richard have been doing on the 
CPM design. Richard has now designed the I2C controller for VME access to the 
TTCrx chip to operate at the extended I2C rate of 400 kbit/s (“fast-mode”), which will 
reduce access times by a factor of four. (The TTCrx documentation claims an I2C rate 
of 1 Mbit/s, but this is not an I2C standard.)
There is a world-wide shortage of Flash memory, and it appears impossible to get the 
preferred 3.3V parts. Richard has now agreed to use 5V parts, which have an identical 
footprint so could be replaced in the future with 3.3V parts if/when they become 
available, without pcb artwork changes.
Gilles has essentially completed the VHDL code for the Hit counting algorithm. 
Simulations indicate the latency to be only 10 nsec.
The ROC still remains to be designed, but the buffer memory VHDL code will be 
copied across from Ian.
Some errors were spotted in the backplane pin-out for the CPM slots and notified to 
Sam Silverstein. Tony agreed to contact Sam to confirm the status of the backplane 
design and to ensure that only the final corrected version (v1.0) was on the web.
The estimated date for a schematics review has slipped from the end of March to the 
middle of April.

7. CMM
Ian reported that the schematics were in progress. Panagiotis Apostologlou is 
currently labelling all the signals on the 860-pin Xilinx device for entering into the 
component library.
There are questions concerning clocking if crate and system summing algorithms are 
combined in a single large device. (After the meeting, Ian, Norman, Viraj and Tony 
discussed this and concluded that partitioning these functions into two separate 
devices was the preferred solution.)
There was some discussion about test procedures for the CMM. CMC daughter-cards 
for the DSS must be designed to receive the 40 MHz (parallel) LVDS data 
(intermediate and CTP sums), and also possibly to source data (intermediate sums and 
CPM hits). An engineer must also be identified to work on this design, presumably as 
soon as current designs have moved to the Drawing Office. We will try to formulate a 
draft scheme for discussion at the next Hardware meeting.
It is hoped to hold a schematics review in early-April.

8. AOB
The order for H-P G-link Tx/Rx chipsets will be placed (CORE money) when the 
exact total number (~200) has been identified from the overall budget spreadsheet.
A further 8 G-link Rx daughter-cards (Bob’s design, but with better coaxial 
connectors – Lemo 00?) will be ordered for the RODs in the Slice Tests.
Bob has compiled a list of the power requirements for the final CP/JEP crates, and 
suggested some suitable supply bricks. Tony will ask Paul Hanke what his group has 
ordered for the Pre-Processor crates, and assess whether we could use something 
similar. If not, we should discuss how next to proceed, as there is quite a large amount 
of work involved in preparing power supply systems to meet all the needs of the Slice 
Tests.
For crate/module cooling in the Slice Tests, old 9U fan-tray systems will be re-cycled.
The CAN-bus system at QMW is now starting to work.
Tony will check with Philippe Farthouat if any of the old prototype TTCrx chips are 
still available, as we are limited to 3 only at present, until the new production devices 
appear. In the meantime, of course, the DSS modules for the CERN ROD integration 
tests can use the old CERN TTCrx Test Cards.

Next meeting - Tuesday 10th April at 14.00 in CR02, R1 at RAL. Refreshments will 
be provided.