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Phase 2 DemonstratorThis second generation bit-parallel trigger demonstrator will be used to study data communication aspects of the final level 1 trigger system. Documents describing the major components of this system include the following. Except where specified, the format is usually PostScript. Description of ModulesFADC modulesDesigned and built by the University of Heidelberg (IHEP)
Timing Control Module
Transmitter ModuleCluster Processing ModuleCrate system, incorporating a special high speed backplaneDAQ software Miscellaneous
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This page was last updated on
16 December, 2013 |