ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 09 September 1999

Minutes

Present: Eric Eisenhandler, Norman Gee, Bob Hatley, Tony Gillman, Viraj Perera, 
Richard Staley

1. DSS motherboard status
Viraj reported that the two assembled DSS motherboards had been at RAL since 1st 
September, and testing has been proceeding on one of them. All FPGAs can be 
loaded correctly, but there are problems with getting VME operations to function 
(no board select signal), which appear to be located in the Xilinx CPLD which 
handles the VME protocol.

2. Link cable assemblies
Bob reported that an order had been placed for ten 10m cable assemblies, but no 
delivery date was yet available. He is still awaiting a reply from the 
distributors regarding the availability from AMP of 20m assemblies (preferable 
for our use) or of raw cable.
Richard reported that he had not yet received a response from AMP to his request 
for technical specifications of the cable material to supply to CERN for 
approval.
The Birmingham technicians have now made two 10m and two 5m cable assemblies 
with BERG connectors, and Richard has already checked the LVDS links with 10m 
and 15m (10m joined with 5m) link cables. Stable lock conditions are achieved 
with the 10m link cable, but not with the 15m cable assembly unless pre-
compensation (100 ohm resistor + 100 nH network - tuned to the cable parameters) 
is applied at the Tx end.

3. G-link daughter-card status
Bob reported that the two assembled Tx daughter-cards will be back at RAL by 
Friday 10th September.

4. ROD prototype specifications document
Norman reported that the "final" specifications document (Draft 7, August 1999) 
is now on the web. Tony will ask the original reviewers to look through it 
again, as there have been a very large number of changes since the original 
version.
Once it has been signed-off, James will start to work on its detailed design 
(assuming he is clear of the DSS work by then).
We will try to learn some lessons from the unexpectedly prolonged timescale of 
the DSS module when estimating the schedule for the ROD prototype design/layout.

5. CP ASIC specifications and PDR
Viraj is awaiting comments from Alan on the algorithm definitions in the most 
recent specifications document.
A schedule for the Preliminary Design Review has been submitted to the Technical 
Coordination at CERN - we are proposing that it be held in November 1999. The 
final documentation must be available by mid-October for distribution to the 
reviewers. The review will be held in two stages - initially by e-mail exchange 
but finally (and most importantly) by having a one-day round-table meeting 
between all the reviewers and designer(s), which would be followed immediately 
by a summary of the proposed recommendations.
It should be noted that for the PDR the important issue of defining the target 
device (ASIC or FPGA) is not mandatory.

6. CMM/SMM prototype - next stage?
Norman will summarise the current status of this work and circulate it to Uli 
and Sam for comments. Another telephone conference may be needed, and it was 
agreed that we must soon converge on a mutually-acceptable solution. The 
specifications of the CPM and JEM prototypes cannot be completed until this 
issue is resolved.

7. Any other business
Bob has completed a preliminary design of the TTC fanout module, and a November 
layout slot has been reserved in the Drawing Office.
Kithsiri is making good progress using his diagnostic software with the TTCvi 
and TTCvx modules in Lab 12. Bob will assemble a VME-based module on which the 
CERN TTCrx test card can be mounted so that the complete TTX chain can be 
studied. Kithsiri will check to see if any standard TTC software exists at CERN 
or Stockholm.


* Next meeting - Wednesday 22nd September at Birmingham University - 10.00 in 
Room S8 (2nd floor), Poynting Building.

Tony Gillman