ATLAS Level-1 Calorimeter Trigger
Hardware Progress Meeting - 22 November 1999

Minutes

Present: Bruce Barnett, Eric Eisenhandler, Norman Gee, Tony Gillman, Viraj Perera, 
Richard Staley

1. LVDS tests and timescale
Richard reported that he had run the links with the Datwyler cable sent by Uli from 
Mainz, assembled into two 15m sections and one 20m section. Results so far are very 
encouraging, with a single 15m cable giving no errors during short runs (statistics-
limited BER of ~10-11). Using the 20m cable, a statistics-limited BER of ~10-10 was 
achieved. Work is continuing to understand the observed effect of receiver crosstalk 
generating errors in one particular channel, which occurs when two cables (8 channels) 
are active together.
It was pointed out that the final tests must demonstrate reliable data transport between a 
pair of modules located in two different crates, preferably in different racks.
Richard was encouraged to issue an interim status report within the next few days, in 
order to keep people informed of progress.

2. Serialiser design status
Viraj summarised the recent work in this area. The final specifications document for the 
Serialiser will be completed by the end of December, and a DSS-based test card will be 
designed to accept the Serialiser FPGA sourcing 160 Mbit/s data into a Deserialiser 
device, also implemented in an FPGA. The latter will be based on the Verilog design 
used for the recent RAL215 ASIC, and will later be incorporated into the front-end of 
the CP ASIC/FPGA.

3. DSS tests and future plans
Viraj reported that two new modules had been tested and were now fully-working. Only 
one week was needed this time, with only a single short-circuit needing to be fixed. 
These modules will next be tested in Lab 12 with G-link and S-link daughter-cards.
Richard will take another pair of DSS daughter-cards to Birmingham to be modified as 
the first pair and tested.

4. ROD prototype design status and timescale
Viraj has made changes to the specifications document to reflect the comments from 
Cornelius, Murrough and Uli, to whom he will reply individually once Norman has 
finally checked and signed them off. The document will then be put on the web and Eric 
will enter it into EDMS at CERN.
James will start working on the design of the data-flow blocks, with Azmat defining the 
VME interface. Norman is currently thinking about what functions the PCI-card co-
processor might provide.
The target date is to complete the entire design by the end of March 2000, which already 
looks rather challenging!

5. CP FPGA specifications, algorithm-coding and PDR
Tony reported that the specifications document for this device has been available on the 
web since for the last two weeks, the reviewers had been notified and the PDR will be 
held hopefully some time in December (date to be agreed).
Norman has been looking into the possibilities of compiling the VHDL model of the 
algorithms directly from C-code, as discussed some months ago, using a ~£1K software 
package from “Frontier Design” which is claimed to be compatible with “Leonardo”. 
There was some discussion about the potential problems that may be encountered along 
the learning-curve for this style of designing (latency, timing issues, compilation 
efficiency, etc.). Using the demonstration version of the software, Norman will code a 
simple form of the algorithms (e.g. a single window), the compiled VHDL code for 
which Ian will be invited to assess.
Details of the software package can be found at:
http://www.frontierd.com/products.htm.

6. CPM prototype specifications and PDR
The LVDS work has held up progress in this area, but it is expected to resume very 
soon. We are aiming for a PDR in February 2000. 

7. CMM prototype – next steps
Norman reported that all the functionality of this module is now well-defined. He will 
draft provisional specifications, which will have engineering details added by 
Instrumentation Department engineers as necessary.
It was agreed that we should now aim for a full “Module 0” specification, and thereby 
possibly avoid another iteration from a reduced-size prototype design. This requires us 
to determine very soon the backplane pin-outs of all associated Processor modules 
(CPM, JEM), as well as the physical form of the VME-bus. It is important that frequent 
consultations with our Mainz and Stockholm colleagues be established.
The outstanding urgent question remains the backplane connector type, which hopefully 
will soon be resolved by the “Connector Task Force” (by the end of December 1999).

8. TCM prototype plans
Tony summarised the changes that had been discussed following the Stockholm 
meeting. The TTCrfo module will now have the full functionality of a TCM prototype, 
and will be located in the Processor (CPM and JEM) and PreProcessor (PPM) crates. It 
will therefore also carry interfacing to the crate CAN-bus, the details of which will need 
further discussions between Bob and Viraj.
Close liaison between all sub-systems will be essential to ensure 100% compatibility. 

9. Prototypes – aim for “Module-0” specifications?
This item had largely been covered during previous discussions. The question of CP 
(and JEP) backplane specifications needs a lot more discussion (point-to-point or bussed 
distribution of TTC signals, location of CAN-bus, definition and location of VME-bus, 
etc.). The commonality of designs (CMM, TCM, etc.) carries major benefits, but also 
imposes serious constraints.

10. Surface-mount re-work facilities
It s generally agreed that access to some such facilities will be essential, especially 
during the prototyping phase. At RAL, it is believed that there are some limited 
facilities for small components available in Instrumentation Department. At 
Birmingham, a solder reflow oven is being purchased which can accommodate larger 
components. Viraj agreed to look into the current situation and future plans in 
Instrumentation Department, and report back at the next Hardware Progress meeting. 
Tony offered to ask Paul Hanke what was available at Heidelberg.


11. Any Other Business
Eric commented that a set of milestones covering the next 12 months should be 
prepared before the end of January 2000.


Next meeting - Wednesday 1st December at 11.00 in RAL Instrumentation Department 
Training Room, R25.


Tony Gillman