The ATLAS Level-1 Calorimeter Trigger

Phase 2 Demonstrator

This second generation bit-parallel trigger demonstrator will be used to study data communication aspects of the final level 1 trigger system.

Documents describing the major components of this system include the following. Except where specified, the format is usually PostScript.

Description of Modules

FADC modules

Designed and built by the University of Heidelberg  (IHEP)

• P. Hanke et al., A Flash Analog-to-Digital Converter for Trigger Tests with the ATLAS Calorimetry RD27 DAQ Note #41, June 1995. PostScript or HQX formats.

Timing Control Module

• The programming model (24 October 1995)

Transmitter Module

Cluster Processing Module

Crate system, incorporating a special high speed backplane

DAQ software

• Runs on a Motorola 68040 processor under the LynxOs operating system.

Miscellaneous

• Proposed Module ID register formats (24 October 1995)
• Proposed DAQ Recording Formats (a,b,c,d,e)
• This is the VME address map

This page was last updated on 16 December, 2013
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