ATLAS-UK Level-1 Calorimeter Trigger Meeting
Thursday 17th January 2002 at RAL
Present: Bruce Barnett, Ian Brawn, James Edwards, Eric Eisenhandler (chair), John Garvey, Norman Gee, Tony Gillman, Stephen Hillier, Murrough Landon, Gilles Mahout, David
Mills, Ed Moyse, Viraj Perera, Richard Staley, Peter Watkins, Alan Watson.
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for summaries for slides (pdf)
Minutes of previous meeting
Are minutes worth the pain? If not, what?........Discussion
CP chip tests using GTM...............................James
Cluster Processor Module............................Richard
Common Merger Module....................................Ian
CP/JEP ROD prototype..................................Bruce
Timing Control Module.........................Eric for Adam
CPM test plans.......................................Gilles
Inventory of what we need and have for slice test......Tony
CMM test plans.........................................Tony
ROD-crate DAQ and readout issues.....................Norman
Offline trigger simulation...............................Ed
TileCal summing amplifier FDR/PRR......................Eric
UK financial situation and how it arose................John
Implications for ATLAS-UK..............................Eric
PPRP review of ATLAS-UK................................Eric
ATLAS week and next joint meeting......................Eric
Any other business
Next UK meeting
Minutes of previous meeting
Are minutes worth the pain? If not, what? - Discussion
Eric pointed out that preparation of minutes has become more of a chore. Minutes
of the last UK meeting are not yet available, and part of the last joint meeting
was not minuted. A suggestion from various people is to try a system in which
each speaker supplies a brief summary. We will try this, and these minutes are
the first attempt.
CP chip tests using GTM - James (slides)
James had tried the CP-FPGA code in the GTM with two different configurations.
Firstly a configuration with a small set of test-vectors built into BlockRAM
was tried, and secondly Ian's setup which reads in BC-Muxed test vectors from
external GTM RAM.
James had succeeded in getting all 108 channels to synchronise (using both
configurations) after some initial debugging and the "hand placing"
of the 160 MHz receivers. All 256 vectors in James's
configuration worked, as expected. With Ian's setup, lots of errors were seen,
but there was no obvious pattern to the problem. James created a third configuration
to capture the BC-Muxed recovered
data into BlockRAM for readout, formerly known as the "Scan Path"
James stated that the use of the GTM was a useful aid to debuggering and should
save time when we eventually get the CPM.
CP Serialiser - Ian
Ian has updated the CP Serialiser design to make it compatable with version
ISE4.1i of the Xilinx software. He has also made a slight improvement in the
design of the clock-tree within the Serialiser, and this has led to a large
reduction in the time taken by the Xilinx software to place and route the design.
The functionality and timing characteristics of the Serialiser are unchanged
by these modifications.
In answer to a question posed previously by Richard Staley, Ian confirms that
the Serialiser can be operated with the 160 MHz outputs at 2.5 V, and all other
IO at 3.3V.
Cluster Processor Module - Richard
Richard reported that the CPM PCB will go for manufacture the end of the week.
However, it was mentioned that the CMM PCB was being held on the placement of
its front-panel mounting holes, which also affects the CPM (see below). Richard
thought this had been resolved, so would enquire.
(For information and added later, the CPM PCB went out for manufacture on Mon
21 Jan and with the correct placement. Expected back 11 Feb.)
Later on in the meeting we mentioned the 'slot adapters' for testing each type
of module plugged into the backplane using DSS. Richard said that CPM slot adaptor
will be ready for Simon at Birmingham to lay out this week. The CMM slot adaptor
is still at the design stage.
The CMM has been held up in the drawing office due to some uncertainty over front-panel
requirements. The CMM must comply with standard IEEE1101.10. Dan Beckett has been
able to obtain most, but not all, of the relevent information for this standard.
As soon as the missing information is obtained, and it is certain that the CMM
is compatable with this standard, the design will be sent to the manufacturer.
Common Merger Module - Ian
CP/JEP ROD prototype - Bruce (slides)
Bruce presented an update on the status of module testing at RAL. All faults
in DSS and S-Link modules, mentioned in an extended list at the last UK meeting
(and the November joint meeting at RAL) have been addressed. Bruce is currently
iterating with James on "DSS-1", which is a problem with the S-Link
receive buffer on the DSS: James has provided a new version of the firmware
which will be tested shortly.
Apropos the ROD, Bruce indicated that, unhappily, it appears that the flow-control
difficulties thought to have been cured are re-emerging under variations from
previous test conditions. These will be investigated in the lab with the help
of a logic analyser and the SLIBOX test card which allows connection to the
module-ODIN interface. In addition, fixes to addressing problems in 'slice'
mode of the ROD necessitated changes in firmware common to slice and RoI mode,
so that new RoI-Data-FPGA firmware needs to be tested as well. The iteration
through the fault list is converging, but the systematic application of soak-tests
has yet to be achieved.
Timing Control Module - Eric for Adam
The status of each of the boards is as follows. TCM Serial Nos. 00 and 01:
have all wire modifications according to the problem reports, all CPLDs
programmed successfully with new addressing scheme, ready for distribution.
Ser. no. 00 tested by Bruce. TCM 02 is in a similar state but has a display
problem (now fixed - ed.). Nos. 01 and 02 will need to be tested by Bruce for
reliable TTC distribution.
Bob Thompson would like to know what to do with the other boards that have
been made for the TCM. After a brief discussion, it was stated that they are
needed for the full slice test at Heidelberg.
CANbus status - Dave
No further progress has been made with the Fujitsu Micro. CAN access is still
unavailable, not sure if this is due to incorrectly formed packets being ignored
by the receiver or due to problems with the receiver or both. This is where
a CANbus analyser would be very useful.
After speaking with the AD reps and the Microchip reps on Tuesday, there is
no further info on the AD micro with on-chip CAN. The Microchip standalone CAN
controller (MCP2510) is available now and one of the low-end CAN-enabled PIC's
will be sampled next month and in full production my March.
CPM test plans - Gilles (slides)
On receipt of the CPM board, low-level hardware testing will be performed:
incoming voltages, internal supply plane,etc. Next step will consist of performing
boundary scan of the different blocks with a JTAG port available. CPLD and FPGA
will be downloaded. Basic VME access will be performed: retrieving motherboard
ID and access to TTCrx.
The next part of the test will be to check that algorithms of the different
chips, CP and Serialiser, are working. With only one CPM board, connectivity
and timing for the CP chip could be done with the help of the playback function
and Dual Port Memory (DP RAM). Simple patterns are loaded in the DP memory of
the serialiser, played back via TTC broadcast and retrieved from the DP RAM
of the CP chip accessible via VME.
The real time path and hit merger will be tested by reading hits signals from
the backplane with a CMM Slot adapter card, similar to the CPM slot adapter
card used for the CMM testing, where data are buffered and sent to a slow LVDS
signal daughter card mounted on a DSS board.
To test the Cluster Finding algorithm,we require external data. They can come
from other CP chips not under test and available on the backplane connector.
A passive board could be designed to re-route signals from the backplane toward
the chip under test.
The Serialiser test requires external data as there is no playback option available.
Those data will be delivered with DSS boards populated with fast LVDS signal
daughter card. Once several CPMs have been
tested this way, 3 of them could be used to test thoroughly the CP chip algorithm,
with their playback memory or with LVDS signals coming for DSS Source card.
With LVDS signals, the realtime data path could be tested and BER performed,
by using CMM or CMM slot adapter. With a ROD board, readout block functionalities
A list of materials required can be found in the slides.
In discussion, it was agreed that James will supply a simulation model of the
CP chip firmware.
Inventory of what we need and have for slice
test - Tony (slides)
Slide 1 shows the sub-system which we will assemble in the UK
(probably at RAL) and thoroughly test/debug/control before integrating it
with PPr and JEP sub-systems in Heidelberg. The items which are not UK responsibility
(TTC-related) are shown in grey.
Slide 2 shows the very large system which will form the "Slice"
set-up in Heidelberg in the latter half of 2002. Again, grey indicates non-UK
responsibility. Slide 3 is self-explanatory.
Slide 4 is a summary table showing 28 separate items for which
the UK groups are responsible, all of which will be required for the final
Heidelberg "Slice" tests. Entries in red indicate that work is still
required for design/layout, manufacture, or commercial purchase, or for testing
(in the case of modules/cards which are already assembled but are still untested,
e.g. the VME Mount Module (VMM). Note that there are now very few design or
layout jobs still remaining - the only design jobs are for the relatively
recent small emulation cards for CMM/CPM/PB testing (CPME1, CPME2, CMME).
(Note: CMM testing continues in next talk.)
CMM test plans - Tony (slides)
Slides 5/6 show the use of the CPM Emulator card (CPME2) and
the CMM Emulator card (CMME) substituting for the CPM and CMM respectively,
when testing the HIT data-paths via the PB. The are connected to the Generic
I/O card (GIO) which resides on a DSS and can source or sink 40 MHz data.
The CPME2 in slide 5 can source data into the top or bottom region of the
missing CPM (feeding HIT data to slot 3 CMM or slot 20 CMM respectively) merely
by inverting the card (the backplane pin-out is different in these two regions),
and all 16 CPM/JEM slots can be tested in this way. Slide 6 shows
the reverse emulation, but now only CPM slots 4, 8, 12 and 16 can be used,
because the CMM backplane connector pin-out is only identical for these four
sources (assuming only a single CMME design).
Slide 7 shows how the use of a CMME and CPME2 sourcing and sinking
data from a pair of GIOs on a DSS can independently test the PB data-paths
for HIT data between a CMM slot and CPM slots 4, 8, 12 and 16, in the complete
absence of in-crate modules. Slides 8/9 show how a second CPM Emulator card
(CPME1) could perhaps be used to check the 160 Mbit/s data-paths between adjacent
CPMs, if the
sourcing/sinking GIO contained the appropriate serialiser/deserialiser firmware.
This needs further thought, but is certainly technically feasible.
ROD-crate DAQ and readout issues - Norman
Norman has been looking at the zero suppression of slice data in the CPRODs.
In the present scheme for the CP, pairs of trigger towers are packed into 32-bit
longwords in the S-Link packets. The longwords are discarded if both towers
contain zero. A simple calculation indicates that the four S-Links per ROD are
around 50 percent capacity when reading 5 slices at 100 KHz when the occupancy
is 5%. This is comfortable.
For the Jet system, pairs of em or hadronic jet elements are packed into 32-bit
longwords in the S-Link packets. The zero suppression is much less effective,
as all eight trigger towers entering the two jet elements need to be zero before
the longword can be discarded. Even after doubling the number of RODs and S-Links,
the S-Links are 80 percent of capacity at 5% occupancy. This is uncomfortable.
Norman will look for a better zero-suppresseion regime, without resorting to
Huffman-like encoding schemes.
Norman also reported briefly on the DIG, which is re-forming. Murrough received
a request to take part in a RoD-crate DAQ working group. We agreed that anyone
receiving such a request should discuss (as Murrough did) with colleagues, and
level-1 calo trigger will select an appropriate representative. This person
should keep everyone informed of what goes on. We will have to decide issues
of authorship of documents produced in such new-style DIG working groups.
Offline trigger simulation - Ed
CMT has been accepted as the ATLAS replacement for SRT, so Ed has started porting
his physics analysis to it. Unfortunately whilst CMT itself is well documentated,
the ATLAS extensions are not. Despite the help from the sw-developers mailing
list, it has been slow going.
Additional problems with old releases no longer working and Athena n-tuple
problems have further hampered work. There is, more than ever, a need for decent
documentation at ATLAS.
Eric showed a list of ASSO actions. The main ones pending in the near future concern
documentation of connectivity between the calorimeters and trigger. Some contact
people need to be named or confirmed, both from our side and the calorimeters.
The most interesting of these concerns the calorimeter calibration systems. The
identity of who is responsible for the LAr receivers should be confirmed (hopefully
Pittsburgh) and, by July, the identity of who is responsible for the TileCal receivers.
ASSO follow-up - Eric (slides)
The outcome of the review raised some critical points. Radiation testing was extensively
commented on. The gain of the minimum-ionising signals from the back sampling,
for possible use in the level-1 muon trigger, seems to be far too low and is in
the noise by the time they reach the end of the long cables. Our gain is set to
8 but for large eta 7 would be better. However, R. Leitner is arguing that this
is not a real problem because as we go to large eta more and more energy is lost
in dead material. So far his simulations are only for 1 TeV jets and pions, but
he will continue with lower energies. His desired conclusion is that a gain of
8 is actually o.k. for us. Finally, the review said that the documentation has
to be properly put together and archived in EDMS.
TileCal summing amplifier FDR/PRR - Eric
John described the background leading up to the current financial crisis in particle
UK financial situation and how it arose
ATLAS-UK was asked to propose savings of 10% by the "SCP4" panel as
our contibution to helping with the current financial crisis. The response proposes
to keep capital requisitions at the original level, cut some TD effort, but to
take most of the cut in travel and M&O budgets. This is in order to protect
Implications for ATLAS-UK - Eric (slides)
The periodic (normally about every two years) review of ATLAS and CMS by the PPRP
(ex-PPESP) is scheduled for 25 March, so plans should be made very soon for preparing
documents and talks. However, this was supposed to be coupled to the university
rolling-grant applications, and due to the current financial crisis the grant
round has been postponed by a few months. Therefore, ATLAS-UK has asked the PPRP
whether 25 March is an appropriate date. No reply has come back yet.
PPRP review of ATLAS-UK - Eric
ATLAS week and next joint meeting - Eric
The next ATLAS week is at CERN, Monday 25 February through Friday 1 March.
So far there is little information about the programme.
The next joint meeting is at Heidelberg, 14-16 March.
There was no other business.
The next UK trigger meeting will be on Thursday, 21st February at RAL. This
is just before ATLAS week, and well in advance of the next joint meeting.
21 January 2002