This page provides information on changes to the calorimeter trigger design made after
submission of the TDR. Information on changes to TDR
Algorithms and External Systems is also available.
| TDR - Pages 124-125,205-207 |
Updated Version |
| Data is transmitted using Hewlett-Packard G-Link chips running at 40 MHz
with 20-bit data width |
LVDS data is carried between 10-bit National Semiconductor DS92LV1021(Tx),
DS92LV1210 chips. Power per 20-bit link is reduced at the Pre-processor from 1.9W to
0.2W and at the em/tau and Jet/energy processors from 2.5W to 0.3W. G-Link use is
still planned for the asynchronous data and RoI readout to RODs. |
| Presented: CERN Level-1 meeting 23-Feb-1999 (E
Eisenhandler) , Calorimeter Trigger Collaboration Meetings at Birmingham March 1999,
RAL July 1999 and Stockholm November 1999. |
| Status: Agreed. Meets approval criteria: for 8 channels over
two 15-metre Datwyler cables connecting two racks, in a 2-hour long run one channel had
one error and the other 7 were error free. Error rate < 10E-12. Similar results
were obtained using two 10-metre AMP cables. However, it is clear that great care must be
taken over noise and clock purity. |
The ATLAS Level-1 Calorimeter Trigger