ATLAS-UK Level-1 Calorimeter Trigger Meeting
Tuesday 3 September 2002 at RAL
Present: Ian Brawn, Adam
Davis, James Edwards, Eric Eisenhandler (chair), John Garvey, Norman Gee, Tony
Gillman, Stephen Hillier, Gilles Mahout, David
Mills, Ed Moyse, Viraj Perera, Alan
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for summaries for slides (pdf)
Cluster Processor Module and CP chip tests...........Gilles
Common Merger Module....................................Ian
CP/JEP ROD prototype...................................Tony
DSS and ROD firmware updates..........................James
TCM, GIO, CAN, Ejectors, TTCrx.........................Adam
Stockholm, Mainz and Heidelberg status...............Norman
Schedule and milestones................................Tony
Online software status
Software status..........................Steve for Murrough
Offline simulation and physics
Trigger simulator and integration status.................Ed
Input connectivity document...........................Steve
TileCal receiver specification.........................Eric
PPRP status report.....................................Eric
LECC talk rehearsal..................................Gilles
Any other business
Dates of next UK meetings
Cluster Processor Module and CP chip
tests - Gilles (slides)
All 20 Serialisers have been loaded with firmware. The dual-port RAM (DPR)
problem of corrupted data appearing from time to time is resolved thanks to
a new firmware version. The CP chip has been downloaded with the CP Scanpath
debugger mode. Four channels were identified as defective. Two of them have
been repaired. They were probably been damaged during early tests, when we were
trying to probe some signals on the board. The two others are trickier to understand.
It appears that the synchronisation is OK for one of them but the data are wrong,
always kept to the same value of 0x8. The other one is even harder to understand.
The synchronisation is not OK for this channel, but as soon as you download
the CP chip with the real mode the synchronisation works correctly for it. A
way to understand the problem will be to download another CP chip and see if
a similar problem appears.
Meanwhile, more tests have been carried out on the CP chip with the real mode.
Threshold values have been downloaded and test vectors sent to its output. A
VHDL testbench has also been run with similar pattern, and knowing that the
fanned-in data from the backplane were all set to 0. The result has been compared
with the results of the CP chips. Unfortunately they disagreed, probably due
to the problems with the two faulty channels mentioned above. Use of HDMC for
these tests is tedious; the CPM module services software will be improved and
that will allow automatic testing to be done.
The VME controller has been modified in order to download other firmware such
as the readout (ROC) controller. DAQ ROC has been downloaded successfully and,
after some debugging, seems to work OK. The data path has not been tested as
it requires a level-1 accept signal. A TTCdec card is needed or the L1A could
be provided by the VME controller, after some modification of the firmware.
More development of software is needed to automate the testing (set CP thresholds,
fill DPR, etc.). In the near future, LVDS receivers will need to be tested with
the help of DSSs.
Common Merger Module - Ian (slides)
Ian reported on the progress of the CMM tests. Most of the real-time data path
has now been tested and shown to work. The GIO and RTM cards have also been
shown to work. No major bugs have yet been found. However, so far no soak tests
have been performed, so any bit errors at low rates will not have been detected.
When the testing of the real-time path on the CMM has finished the logic to
load the FPGAs on power-up will be commisioned. A new design iteration of the
CMM will then be produced to correct for all known PCB errors. At this stage,
Ian said, the existing CMM could be made available for tests with other modules.
Norman and Tony responded, however, that it would be more useful to continue
the tests in the Electronics lab.
Tony also asked whether the quality of signals transmitted long distances on
the backplane had been examined; Ian said not yet.
Steve asked which 14 of the 16 'algorithm' slots in the crate were assumed
for the CPMs, and it seemed that there might be a misunderstanding since the
CPMs should be in the central 14. Ian would check and fix if necessary.
CP/JEP ROD prototype - Tony
Most of the recent tests were done with the original ROD - serial #2. A major
concern was the frequent non-repeatability of results, with classes of errors
varying from run to run. Several problem areas were identified:
- Male-male header blocks linking TTC Interposer card to ROD.
- Mother-board must have correct diameter pins (~100 pins in total) - if
too large, contact is intermittent.
- There is some evidence that some of the female socket pins on the original
Interposer have been damaged by using the wrong diameter header pins
- For the remaining RODs, new Interposers should be used, so more need to
- Daughter-card mounting is not always safe - insulated pillars or protective
insulated washers should be used to avoid possible shorts on the ROD mother-board.
Adam Davis is sorting out a better system.
- There are still intermittent errors after all these fixes, especially when
mechanical movement of the DSS (mother-board and/or daughter-cards) occurs
during a data test run.
- Swapping or substituting the G-Link daughter-card or the S-Link cable does
not fix this problem.
- Substituted the optical for electrical S-Link daughter-card, but there
is a mechanical mounting problem with its optical connectors, requiring removal
of its front-panel to allow fitting through the ROD front panel. Also, they
are not planar with the mother-board
Even after these changes, mechanically disturbing the DSS still induced errors.
The next step will be to exchange the DSS and/or its CERN TTC Card.
Several classes of errors were observed:
- ROD remains permanently busy, because it apparently has not completely
emptied its data, which could be caused by a failing G-link channel.
- "SANITY CHECK" - apparently meaning an error in the structure
of an event (e.g. last word in the DSS memory not being an End Of Fragment,
or fragments missing start/stop markers, etc.)
- Comparison of sink with source data reveals errors - much more analysis
is needed to understand this.
- The test aborts itself for no apparent reason
A lot of work will be needed to commission the six new RODs.
DSS and ROD firmware updates - James
All DSS modifications are up to date. CMM CP slice design has
been ready for some time and is awaiting testing by Bruce. James has started
JEM slice design to draft spec 3.0. Work stopped on 22nd August 2002 after meeting
with Norman, due to too many uncertainties. Now up to draft 6.0. Work will not
commence until spec signed off. JEM RoI design work will not commence until
spec sign off. A lot of work has been done, but was destined to end up in the
TCM, GIO, CAN, Ejectors, TTCrx - Adam (slides)
TCM - The problem displaying the VME data when accessing other
modules in the crate has now been resolved, the memory has been extended to
allow more space for CANbus, and a new version of the firmware along with documentation
on how to up-date the module will be available on the web as soon as possible.
GIO - The cards are being used successfully by Ian to test the
CMM. Another four will be ordered when appropriate circuit modifications have
CAN - The TCM has now been set up to request temperature and
voltage data from the CMM, the CMM responds and it also alerts the TCM of an
over-temperature situation or problem. The next step is to create a program
for the CPM and the TCM.
Ejectors - New ejectors from Elma UK have been sent for evaluation
and are currently undergoing a trial at RAL with a CMM. A new cutout is required.
TTCrx - Adam has obtained the Verilog file and compiled it using
Modelsim for various addresses.
Stockholm, Mainz and Heidelberg status
- Norman (notes)
In Heidelberg, Karsten has completed his thesis. His MCM tests show digital
output consistent with the input analogue pulse, but the parity seems wrong
when the digital data are all zero. He will join the HD group as a PhD student
after a pause to recover, and do systematic MCM tests to check digital output
with analogue input from the video memory. Ralf is developing VME tests of ASIC
using Labview - so far the ASIC registers are in their default power-up mode.
Paul is writing some C++ code within the simulation framework, which will be
needed to interpret digital output from the MCM. The main move to the new building
will be on 16/17 September.
In Mainz, a new DSS daughter board with the 6-channel LVDS receiver chip has
been designed and is ready for manufacture. LVDS links using the new chip should
be tested before using it in the new JEM in place of the existing 4-channel
device. Two pairs of LVDS Tx/Rx cards will be tested at RAL with the current
HDMC and DSS, and then one tested pair will be sent to Mainz. Uli already has
two LVDS Tx cards. When the LVDS test is complete, Uli will resume JEM studies.
The 80 MHz paths on the JEM have been timed-in, and the readout firmware
rewritten to match the latest slice formats. Andrea has driven signals down
the G-Link, which locks at the receiving end, but the data has not yet been
In Stockholm, where Sten is now resident, Attila has improved the jet algorithm
firmware speed to 110 MHz by changing comparators to be fully parallel
and adding extra flip-flops (+12.5 ns). The design will be back-annotated,
then tried with test vectors. A JEM + crate etc. could then be used in Stockholm.
RAL to check on the status of the crate sent recently; it should be assembled
at Birmingham and returned to Stockholm. Daniel and Åsa have decided to
work within the common simulation framework.
Schedule and milestones - Tony (slides)
We have an exceptionally tight schedule over the next six months, leading up
to the Heidelberg Slice Tests. Although the standalone module testing is going
well, with no significant problems found so far, nonetheless the work to be
completed before the CP sub-system is assembled and ready for its "data
challenge" is considerable. We have stated that the CP sub-system will
be available for this stage of testing by early-October, at which time the JEP
sub-system should start to be assembled at RAL. Both of these sub-systems must
be thoroughly tested and understood before we would feel confident of shipping
them to Heidelberg for interfacing to the PPr sub-system in early-March next
A large number of milestones have been defined to ATLAS management over the
next two years, eight of which (should) occur before the end of next year. During
this period, the revised JEM0 design will be under way, and a light-weight FDR
is planned for late-October. During the period of the Slice Tests, the 9U version
of the CP/JEP ROD will be designed. There is a post-Slice Tests period of design
iterations of all other modules in Q3 2003.
There will be an extensive series of FDRs/PRRs during Q1 and Q2 2004, with
full-scale module production running through to Q4. During 2004 there is a strong
wish to carry out Trigger-DAQ integration tests in the ATLAS Test-Beam.
The full CP and JEP sub-systems will be tested throughout 2005 before installation
and integration with the commissioned PPr system in USA15. Six months of in-situ
testing are provided in the schedule, to end with the full trigger available
in Q2 2006.
Online software status
Software status - Steve for Murrough (slides)
An overview of the progress since Stockholm was given under Murrough's usual
headings. Firstly the general aims were presented, together with their status
with respect to the testbed DSS/ROD system tests. Many of the targets of integrating
ATLAS software, our test and simulation infrastructure had at least been demonstrated
at some level, although no ROS integration had been recently tried. There is
however much work to be done in polishing the software and extending it to more
The progress in most software packages was presented. A major area of development
was the finalisation of a new HDMC composites syntax within the module services
and CMT structure - work done by Bruce. Much development had also been done
in the simulation area, particularly in integrating with run control and system
tests. This work has implemented the test scheme proposed back in February,
although many details had to be worked out over mini-workshops and phone conferences
since. This work had led to the successful integration of several strands of
the online software, although more integration work was needed.
On software organisation, the use of CMT for the RAL CVS repository has been
honed by Murrough, and a recent useful addition has been a nightly build and
a build status web page. Finally the status of the evolutionary delivery of
software as presented at Stockholm was summarised. The early parts of integration
for the DSS/ROD tests seem to be going well, but it is becoming clear that software
for CP sub-system tests is still a little way off.
Simulation - Steve (slides)
Since the last report back in March, much progress has been made on many fronts,
particularly in the integration of the simulation into the rest of the online
software world. Highlights include the migration to CMT, development of common
level-1 calorimeter tools (such as TTC information needed by all module simulations),
improvement of the CPM and CP/JEP ROD simulations, the development of a common
test-vector reading scheme for hardware and simulation, and most importantly
the integration with the online database and run control.
The result of all this work was that now the simulation could be performed
under the control of the standard ATLAS run control interface and it would take
essentially all its information for setting up the simulation from the database.
This produces a way of interacting with the simulation which is unified between
the hardware and simulation. A scheme for generating test vectors has also been
writen to interact with run control in a similar way. Again the specifications
of the generation are entirely governed by the database.
The application of this new software to the DSS/ROD system was illustrated
and the results of recent initial tests with the hardware at RAL were given.
Unfortunately, since the hardware was not in a working state, the exact correctness
of the simulation test framework could not be tested, but results seemed to
indicate that the new software was working at least as well as the original
test setup. More work with a working hardware configuration would be needed
to fully test the software.
Finally, future plans were presented. The most important immediate work was
to complete the ROD tests and try to transfer the software framework to start
testing the CPM at Birmingham. In other news, Paul Hanke has started work on
the PPM simulation, and the Stockholm students are continuing work on the JEM
using the common simulation framework.
Calibration - Norman (slides)
Murrough, Norman and Thomas are working on a document, intended to be a joint
publication with calorimeter groups. It should describe which calorimeter calibration
systems are used, how the systems interact, and how the calibration is steered.
Apart from this, Eric and Norman have started a discussion on the calculations
and decisions that the software needs to perform. The overall algorithm must
always generate values for all our parameters for all reasonable calorimeter
states, correctly handling dead cells. As we are the only users of tower-summing
circuits, we will need to keep our own lists of defective parts of the system.
Monte Carlo studies will be needed to justify choices when handling faulty cells
- e.g. it is probably desirable to turn off dead, oscillating, and uncalibrated
cells in the LAr, but should we change LUTs or thresholds to compensate? And
what do we do in calorimeters where loss of a cell can be a big fraction of
We also need to start developing some algorithms and code to extract peak
timing, energy, and BCID coefficients from a sampled analogue pulse. We need
to know how CPU intensive they are, to complete the agreements with calorimeter
groups on the calibration mechanisms. We will also need, quite soon, code to
optimise the internal timings in the trigger system.
Offline simulation and physics
and integration status - Ed
Ed reported that the energy triggers are still being debugged, but is almost
ready. A RoIDecoder has been written for LVL2, and some example code created.
There has been further integration with the CTP sim, and Ed feels he is almost
finished. Alan has started validating the simulator.
Input connectivity document - Steve
There has been little work done since May, when things were actually looking
in quite good shape. Since then, more information from Bill Cleland has meant
that updates to many of the Excel spreadsheets are needed. Murrough has done
this for his documents, but Steve has yet to do this. Also there is still no
text framework for the diagrams.
TileCal receiver specification - Eric
Eric has started on a specification, but has made no progress recently due
to other work. To finish he needs some information from the input connectivity,
but the crucial point concerns the issue of input coupling. We need to decide
whether we can get away with the same transformer coupling at the input as the
liquid argon, and that is where we need some analogue expertise.
PPRP status report - Eric
Eric presented information about the status report that must be submitted to
the PPARC Project Peer Review Panel on the past three years of work on ATLAS
in the UK. He described the state of work on the document to be submitted, on
the talk at the open presentation on 30th September, and some of the issues
surrounding discussions on what additional resources to request.
LECC talk rehearsal - Gilles
Gilles rehearsed his talk for the LECC Workshop in Colmar the following week.
There was no other business.
The next UK trigger meeting was tentatively set for Thursday, 17th
October at Birmingham.
17 September 2002