ClusterAlg.gif (577 bytes) The ATLAS Level-1 Calorimeter Trigger

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ATLAS-UK Level-1 Calorimeter Trigger Meeting

Wednesday 15 May 2002 at RAL

Present: Bruce Barnett, Ian Brawn, Adam Davis, James Edwards, Eric Eisenhandler (chair), John Garvey, Norman Gee, Tony Gillman, Gilles Mahout, David Mills, Ed Moyse, Viraj Perera, Richard Staley, Peter Watkins, Alan Watson


Click this side                               Click this side
for summaries                                for slides (pdf)
Hardware status
Cluster Processor Module and test cards.............Richard
Cluster Processor Module and CP chip tests...........Gilles
Common Merger Module and DSS I/O cards..................Ian
CP/JEP ROD prototype..................................Bruce
Timing Control Module and VME Mount Module.............Adam
CANbus: status and overall scheme......................Dave
Stockholm, Mainz and Heidelberg status.................Tony
Software status
Brief highlights of April T/DAQ week..................Bruce
Draft document on software overview..................Norman
Trigger simulator and integration status.................Ed
General items
ASSO follow-up.........................................Eric
Coming meetings
ATLAS week, joint meeting, T/DAQ workshop..............Eric

Any other business
Dates of next UK meetings

Hardware status

Cluster Processor Module and test cards - Richard (slides)

CPM: JTAG testing was invaluable. Manufacturing faults were detected and corrected. However, test coverage was not 100%, with the following items omitted from the test: backplane connector, LVDS receivers, GLink Tx, and CAN controller. For production testing we need an additional PCB with boundary scan (BS) devices, which plugs into the connector. Viraj suggested a useful simplification by looping backplane outputs back onto the board, as both source and sink are BS devices. Richard replied that we still needed a BS device to check the VME and Hit interfaces.

The VME interface is now working as intended, but having problems with Geographical Addressing (GA), which has temporarily been disabled so that that testing may progress. Richard also reported the CAN controller running hot. On the CMM, Ian mentioned the CAN controller was corrupting the GA signals, so the two problems may be related. Note added later: This was found to be true of the CPM. The CAN controller overheating was due to an unsoldered lead giving intermittent connection of the crystal oscillator. Now fixed, it runs cool.

The CPM had some wrongly specified clock-buffer PLLs in the schematic which inadvertedly doubled the frequency of certain clocks to 80MHz. Note added later: These have now been replaced and all clocks are now distributed at 40MHz as intended.

The Flash RAM controller is working, with software able to read, write and erase Flash RAM contents used to hold the FPGA configurations.

In discussion, Norman and others were concerned about the module flexing when inserted into the crate. Richard said he would try to find a solution.

Test cards: One of each of CPM and CMM slot adapters have been built. More would be made for the UK and also for the Mainz. Richard will design a small PCB for looping back the CPM FIO signals.

Cluster Processor Module and CP chip tests - Gilles (slides)

Tests on the CPM have started. The setup is made of one L1 calo trigger 9U crate and a 6 U crate mounted on a rack. The 9U crate holds a VMM, a TCM and a CPM and the 6U a Concurrent single-board CPU, a Bit3 board and TTCvi/TTCvx. Communication to 9U crate is performed with a second Bit3 plugged into the VMM. A small code has been written to map VME addresses between these two crates via Bit3. Such a setup enables us to switch off the 9U crate without rebooting each time. An HDMC part has been written to download the Flash RAM of the CPM but has not been tested yet. But the tests have been very successful so far: TCM ID, CPM and firmware ID have been retrieved. Control Register has been written and the FIFO to access Flash RAM is working. The trouble comes from the GeoAddr, which does not seem to work, so the firmware has been modified to bypass its input pins. Next steps will be to download one Serialiser FPGA, check everything is working during the downloading, and perform tests. All CP chips and Serialisers will then be loaded and tests of connectivity at high speed, and calibration performed. A loop- back board, covering a part of the backplane connector to send back signals to a CP chip under test, would have to be done. This first stage of debugging the CPM was mainly debugging firmware. Therefore, a version of the VHDL Serialiser chip model to B'ham will be desirable to help debugging the Serialiser chip algorithm in the future.

Concerning the CP chip simulation at B'ham, previous simulation were done with a model without taking into account the choice of the device. Previous measured latency could be too optimistic. Now two files are available to make such a more realistic simulation, but the present program does not seem to work correctly. Too many warnings are generated, which stops the simulation. Things are under investigation but it has been noticed that there was a delay of 15 ns between a CS inserted and before data were available on the VME data port. James said it's not a problem and you will have just to stretch the R/W strobe by an extra 15 ns or more.

In discussion, Norman asked which problems in this initial testing need to go into the QA system.

Common Merger Module and DSS I/O cards - Ian (slides)

Work on the CMM is progressing. A number of bugs have been found and resolved, as detailed in the presentation. The CMM will be given to PPD in June, so that they may play with it. Two further types of card are necessary to fully test the CMM: the GIO cards for the DSS (to sink and source LVDS signals) and the Rear Transition Module (an interface between the CMM and SCSI-3 cables). Four GIO cards have been manufactured and are currently being assembled. The dimensions of the RTM have been established and it is currently being laid out by Panagiotis.

In discussion, Eric remarked that the specification document lacks the pinout details of the front-panel CTP connector.

CP/JEP ROD prototype - Bruce (slides)

Bruce presented an update on the status of tests with the CP/JEP Rod. The recent focus has been on the completion of new software in order to hasten progress with the so-called "module-services" package(s) whose definition is required for s/w progress with other modules. The test software now uses the new "module-services" classes. In the regime of firmware, no new problems have been identified, but the status needs to be reviewed. New firmware variants for the DSS will appear soon, and the tests of these will need to proceed, using the ROD-DSS test setup in R12.

Timing Control Module and VME Mount Module - Adam (slides)

Working closely with Dave Mills has produced some code to further the testing of the microcontroller on the TCM. Just the CANbus needs to be tested now.

The VMM look like it might actually fit into slot one, comments that it would not were due to a mistake on assembly first time round. It has been decided that the crate number will be set by the switch on the backplane rather than the VMM. Note that the LED's indicating the geographical address are inverted..

CANbus: status and overall scheme - Dave (slides)

David gave a brief overview of CAN again, and how the crates are connected in the CAN network. The Fujitsu is now able to communicate with the VMEbus via the DPM. Work is continuing on the CAN interface. New tools have been acquired from Fujitsu and these have been distributed to all interested parties.

Stockholm, Mainz and Heidelberg status - Tony (slides)

Heidelberg status: As there were no callers (German holiday), this is a brief status based on the Heidelberg group meeting minutes from 3/5/2002, so is not fully up-to-date. They have two fully-assembled MCMs ready for testing, for which several test modules/cards are ready for manufacture. Two AnIn daughter-cards (as will be used on the PPM itself) are ready for assembly. Progress on the VME motherboard for the LVDS Rx card – data I/O state-machine code now working. They have updated their Xilinx synthesis tools.

Mainz status: JEM0.1 testing continues with real-time data-paths. Continuing problems with input data synchronisation, but currently bypassed to enable work on data-path into main processor FPGA. An LVDS Replicator (fan-out) module is being made to enable multiple channels to be populated. Running the RAL DSS under the HDMC framework causes problems. It is suggested that these may be caused by the VME LINUX driver – this will be discussed further at the next software meeting. In-crate operation of JEM0.1 is at least one month away.

Stockholm status: Longer crate runners will be delivered w/b 13th May. At around the same time, ground-pin cable assemblies will be shipped to RAL and to Birmingham for fitting to crates #1 and #2. Crates #3 and #4 will be fully completed in Stockholm before shipping – it was suggested after the meeting that #3 be shipped to RAL to allow a second test system to be operated. The UNIX system in Stockholm is currently being upgraded. The latest Slice Test schedule was discussed and approved. Another new graduate student could help with JEP sub-system tests in the UK later this year.

Software status

Brief highlights of April T/DAQ week - Bruce (slides)

Bruce presented a view of some of the highlights from the T/DAQ week which took place recently at CERN. Many issues were touched upon. As original transparencies are also available on the web, the talk was meant to give a flavour and overview. A special session outlining the nature of the new T/DAQ management was not summarised, but details are also available on the web.

Also pertinent, but not extensively reported, was a Level-1 Dataflow meeting which took place during the workshop. At that meeting progress with the RoI-Builder was discussed – in particular issues pertaining to flow control for that system. The means of interaction of the RoIB with the Busy logic of the trigger will form an important part of the RoIB design. It should be remembered that it was the issue of flowcontrol which precipitated many of the difficulties which were encountered at the L1-calorimeter/RoIB integration tests of early 2001.

Draft document on software overview - Norman (slides)

In response to questions from Oliver Nix, Norman had started work on a system software overview document. Based on R0D-Crate DAQ terminology, Norman described the hierarchy of connections from workstations, connections between run controllers, and the interactions between the run control and the module services for each physical module. The document also describes how test data is generated and used in test runs. Overall, the database emerges as a key control component needing a lot of detailed work.

In discussion, Pete requested that the L1A-simulating scheme with DSS be written up.


Trigger simulator and integration status - Ed (slides)

Ed reported that the jet trigger simulation is finished (but not tested) and that work has begun on the energy trigger. He has agreed to produce a 'ROD' simulation and various associated utilities to aid LVL1/LVL2 integration, and this is almost done. Ed summarised the output of TrigT1Calo, and then listed what work remains (integration with TrigT1Calo, Energy Trigger and validation), finally giving some idea of a timetable over which this will occur.

General items

ASSO follow-up - Eric (slide)

Eric showed a slide listing the current status of ASSO actions relevant to our project.

  • A person to look at overall timing of the experiment has been named: Kinihiro Nagano
  • Connections from calorimeters to the trigger have been documented by Murrough and Steve; the work is almost finished. Eric remarked that it should be reviewed, or at least read critically, by some people who have not been involved.
  • No official word yet on whether Pittsburgh can build the receivers; after the meeting communication with Bill Cleland reminded us that we need to write a specification for the TileCal receiver signal-handling.
  • Calibration contact people are as follows: from the trigger, Thomas Trefzger; from LAr, Pascal Perrodo and Isabelle Wingerter (both LAPP); from TileCal (for the time being) Rupert Leitner.

Papers - Eric

John's abstract has been submitted to the big ICHEP conference in Amsterdam. It should be put on the web. Gilles' abstract and summary has been submitted to LECC in Colmar and is already on the web.

Coming meetings

ATLAS week, joint meeting, T/DAQ workshop - Eric

There is supposed to be a level-1 trigger status report at the ATLAS overview week in Clermont-Ferrand, but no one from the calorimeter trigger seemed to be going. Eric had asked Sam if he could do it, and also it turned out that Pete is going. So one or the other will give the talk.

For the joint meeting in Stockholm on 4-6 July, the main meeting will probably have the usual layout. A problem with the software session that often occurs on the Thursday morning is that a number of people will not be able to travel out on Wednesday evening due to the retirement celebration for John Dowell in Birmingham. Eric will try to see if a software meeting is necessary, and if so whether Saturday afternoon is ok.

Norman will go to the July T/DAQ workshop.

Any other Business

There was no other business.

Next UK meeting

The next UK trigger meeting will be on Tuesday, 18 June at RAL.

Eric Eisenhandler, 30 May 2002

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