ATLAS-UK Level-1 Calorimeter Trigger Meeting
Thursday 18 June 2002 at RAL
Present: Bruce Barnett,
Ian Brawn, Adam
Davis, James Edwards, Eric Eisenhandler (chair), John Garvey, Norman Gee, Stephen
Hillier, Murrough Landon, Gilles Mahout, David
Mills, Ed Moyse, Viraj Perera, Richard Staley, Alan
Click this side Click this side
for summaries for slides (pdf)
Cluster Processor Module and test cards.............Richard
Cluster Processor Module and CP chip tests...........Gilles
Common Merger Module....................................Ian
CP/JEP ROD prototype..................................Bruce
DSS and ROD firmware updates..........................James
TCM, VME Mount Module, GIO cards and CAN...............Adam
Stockholm, Mainz and Heidelberg status.................Tony
Schedule and milestone schedule........................Eric
Calibration and calorimeter discussions at CERN......Norman
Simulation and physics
Trigger simulator and integration status.................Ed
TileCal cables and input connection document.......Murrough
TileCal receiver specification.........................Eric
ATLAS week, Stockholm meeting, T/DAQ workshop..........Eric
Amsterdam and LECC papers.......................John/Gilles
Any other business
Dates of next UK meetings
Cluster Processor Module and test cards -
CPM: Module clock distribution is working. VME interface is functioning,
with access to ID , Revision No, Control and Status registers. FLASH memory
controllers are giving reliable R/W and Erase operations, and have been used
to sucessfully configure all Serialiser FPGAs. Serialiser control registers
are now accessable from VME.
The CAN microcontroller is now running cool; overheatingwas caused by an unsoldered
pin giving intermittent connection with crystal causing chip to run in a strange
mode. This fault mode also caused the microcontroller to corrupt the module's
internal Geographical Address lines.
The CPM's FPGA configuration circuit is not ideal for development circuits
or dealing with fault conditions. All the FPGA configuration 'DONE' signals
have been 'wire-anded' as suggested in various Xilinx application notes. However,
should one or more FPGA not be configured, then this line will stay inactive
even though all the other FPGAs have released the line. The configuration process
will stall until this line goes active. However , the default configuration
behaviour can be modified and the FPGAs made to 'wake-up' before releasing DONE.
The next revision of CPM will condition the individual DONE signals to isolate
any unconfigured part. The present FPGA Configuration Controller sends a fixed
number of bytes to the FPGAs, not relying on the DONE signal.
There is still no solution to the mechanical strengthening of the module.
The next task is to use the Serialiser to play back 160 Mbit/s data. This
requires the TTCrx controller to be working, which sources the 'EnPlayback'
signal. We will attempt to configure all remaining FPGAs, and then test the
TTCrx interface, for which we need a TTCdec card.
Probingthe module inside a crate is very difficult, and one solution is to
build a 'pizza-box' style test crate, which horizontally holds the module under
test, VME-VME link, plus a VME-- backplane with a suitable power supply. There
was some discussion on how one could have better access with two adjacent modules
under test, and the feasibility of building extender boards.
Summary. Making steady progress.
Cluster Processor Module and CP chip
tests - Gilles (slides)
The decision to download only one FPGA serialiser instead of all 20, has caused
some problems due to the interconnection of the DONE signal between all of them.
The FPGA toggles from its configuration state to its operational state once
the DONE signal of all other FPGAs has also been pulled up. This problem has
been by-passed by generating dummy Serialiser firmware with the option to not
ask for the DONE signal to go high. Once the dummy firmware has been proven
to work correctly in the one FPGA under test, the 19 others have been downloaded
and then the serialiser file itself has been loaded.
First VME access showed that registers were readable and writable. The firmware
ID seems to be set to 0, as was seen during local simulation test. The dual-port
RAM inside the serialiser is not accessible yet, the En-PlayBack signal coming
from the TTCrx controller is not generated correctly. The controller has to
In order to download FPGA binary files, a new HDMC part has been written. This
part, for the CPM only, reads a bit file, swaps each byte, and loads them into
a flash memory via a FIFO. On VME request, the file is then passed to the FPGA.
More parts have also been written for future tests: DatasourceTV, which reads
an external file of test vectors to be download inside a RAM, and ModuleI2Cregister,
reading and writing to TTCrx registers via the I2C interface implemented in
the TTCrx controller.
The next step will be to download data in the RAM, download the CP chip with
the ScanPath configuration, and check the validity of the transfered data.
Common Merger Module - Ian (slides)
Further problems with the FPGA DLLs have been encountered. One DLL was losing
lock due to a dirty input clock signal, caused by beating between the 40 MHz
system clock and a 25 MHz clock supplied to the I2C controller. Both of these
clocks are currently provided by crystal oscillators. The problem has been solved
temporarily by removing the 25 MHz oscillator.
Firmware has been produced with a playback functionality slightly different
to that described in the CMM specification. Using this firmware, data has been
loaded into the Crate-FPGA playback RAM, transmitted via the real-time data
path to the System FPGA, and read from the System-FPGA playback RAM successfully.
Firmware has also been produced for the FLASH-controller CPLD that will load
the System FPGA with the contents of the FLASH RAM. This firmware has been simulated
successfully but has yet to be tested in hardware.
In discussion, Norman pointed out the importance of using the TTC rather than
a crystal as clock source.
CP/JEP ROD prototype - Bruce (slides)
Bruce presented an update on software and firmware status of items concerning
the CP/JEP ROD. On the software front, code has been moved into repositories
(CMT in the case of the moduleServices) to make public access possible. Integration
work (towards a model comparable to that to be used in the slice tests) in conjunction
with Murrough has incorporated the online database into the CP Rod test programme.
A number of items here are pending, in particular the restructuring of test
code into a "looper/kicker" pair of processes, and later incorporation
Concerning firmware, much new DSS firmware is available (see James' presentation
below) and will need to be tested in conjunction with the ROD.
Bruce outlined plans to set up a test-bench for use by others in pre-slice
tests of the sixnew RODS which have been produced.
DSS and ROD firmware updates - James
James discussed the contents of Project Change Order 001 for the
DSS, which can be downloaded from here.
He briefly explained the various modifications and added features required for
future ROD and GIO tests. Some of the changes are to provide memory wraparound
that will allow capture of data on level-1 accepts.
In discussion, Norman pointed out that someone should update the
module specifications to reflect these changes.
TCM, VME Mount Module, GIO cards and CAN - Adam
TCM - It has been noted that there is a problem with the TCM
latching data from the backplane when accessing other modules. A new firmware
version of the "VME decoder" and "data-latch-Visualisers"
will be issued as soon as the problem has been solved.
VMM - The VME Mount Module has the problem of identifying what
reset is performed when the front panel switch is pushed, and also the geographical
address LEDs displaying the complement of the address. There may be a fix to
both these problems, further development is required.
GIO - A mistake has been made when placing the components on
the board and as a result, all of the CMC connectors are 180 degrees out. An
adapter card is being manufactured and will be here by the end of this week
or beginning of next. However, the card has been powered up and we can connect
to the board via JTAG and see both PROMs and FPGA, we can also program the FPGA.
The board has not been boundary scanned as yet but it will be when the adapter
CAN - Adam has managed to establish CAN connection between the
CMM and TCM using the backplane of the processor crate, and he has further developed
the code such that a network of three microcontrollers has been set up utilising
the remote request facility of the CAN protocol, one master and two slaves.
Bruce suggested that future versions of the TCM might have CAN status lights
for each module. Norman suggested that we try to capture all comments of this
nature so that future modules incorporate all of the good suggestions.
Stockholm, Mainz and Heidelberg status
- Tony (notes)
In Tony's absence there was no formal talk. Eric and Norman briefly described
the last monthly hardware phone conference, but since then the notes have appeared
and the reader is referred to them.
Schedule and milestone schedule - Eric
Eric pointed out that a lot has changed. Our timetable has slipped,and the
LHC and the ATLAS completion dates have also slipped. Now that we have some
idea of the new LHC schedule, we should re-think and update our own schedule
and milestones. Tony has made a start on the UK part of this (see previous meetings),
but we need to finish the job for the entire project and feed it into the ATLAS
monitoring system. We have agreed with Nick that a new schedule and milestones
would be discussed and approved at Stockholm.
Software status- Murrough (slides)
There has been software progress on several fronts. The HDMC CVS repository
has now been moved to RAL. Gilles has been developing new HDMC parts for the
CPM. The module services packages have now been released as CMT packages, and
development of the CMM module services has begun. Integration of the module
services with the database has started, though there are still some outstanding
problems. The database classes have been extended to cover all the UK modules.
Some progress has been reported from Stockholm on the JEM simulation, and work
on moving the simulation into CMT has started. However more work is required
to integrate the simulation with the database and the run control.
The software group should try to make a more detailed timetable, and also do
some software training.
Calibration and calorimeter discussions
at CERN - Norman (slides)
Norman reported on discussions between himself, Murrough and Thomas, and calorimeter
calibration contacts Rupert Leitner and Bob Stanneck (TileCal), and Pascal Perrodo
and Isabelle Wingerter (LAr) during the recent DIG training week.
The TileCal has a caesium source, a laser pulsing system, and a charge injection
system. We would probably use the charge injection, which can generate 3050k
events from 1800 GeV per calorimeter cell in two minutes. The TileCal
group have not so far developed a run control strategy for this sytem, and are
very flexible about working together in a combined run style.
The LAr has a charge injection system which runs at 10 kHz covering a
range of amplitudes, gains, patterns, etc. The system is controlled by a dedicated
hardware calibration board which uses a Busy handshake with the LAr RODs. There
is no use of the online run control system planned to handle the runnung, and
more work is needed to understand how the trigger can interact with and use
It was agreed to prepare a (3-way) joint document to collect and define the
different procedures. Norman prepared a skeleton which Thomas will populate
for the Stockholm meeting, in part using information from Murrough's earlier
draft calibration note. There will be an opportunity for everyone interested
to contribute to the ideas.
Norman also mentioned new ideas for a possible combined run with detectors,
TDAQ and trigger in 2004. His proposal to ask TDSG to discuss this was endorsed.
In discussion, it was agreed that the ambition level of such a test has to be
kept in line with what can be achieved, that many goals do not actually require
beam, and that many cross-interface tests can be factorised out and tested beforehand.
Simulation and physics
Trigger simulator and integration status
- Ed (slides)
Ed summarised the current status of TrigT1Calo simulation. The ROD is almost
complete with only S-links left to implement. A new RoIDecoder class has been
introduced which returns coordinates from RoI words. The energy trigger is started
and work has begun integrating TrigT1Calo with TrigT1CTP.
The simulation is needed for Data Challenge 1, and so needs urgently to be
Secondary RoIs - Alan (slides)
The distinction between "primary" and "secondary" RoIs
was reviewed. In a typical trigger menu, some thresholds may be used only for
creating secondary RoIs, i.e. will not contribute to the level-1 decision. Nevertheless,
the multiplicities of objects passing such thresholds will be reported to the
CTP (which will not use the information). This is not a problem provided we
have sufficient thresholds, and this usage was included in estimates of the
number of thresholds we would need. Should a future trigger menu demand more
thresholds than we anticipated, it should be possible (with firmware and software
changes) to provide non-trigger RoIs which do not use up part of the "hit
multiplicity" traffic to the CTP. This option will be kept in reserve unless
TileCal cables and input connection document
- Murrough (slides)
Cables - A meeting with TileCal people was recently held at CERN.
They promised to provide more detailed information about signal cables and pinouts.
Due to space problems, it is now suggested to combine the calorimeter and muon
trigger signals on a single 16-pair cable, at least from the extended barrel,
which would be split at a patch panel in USA15. This solution has the advantage
that we could use the same type of cable as the LAr, and so is very attractive.
It would also make the choice of whether we need a patch panel before the receivers,
since in this option we would.
The TileCal group suggested that we bring some of our electronics to their
2003 test beam. This would be difficult for us in view of the slice test.
Cabling document - Some feedback and corrections on our spreadhseets
have been received from Bill Cleland. These have yet to be incorporated. The
text part of the document is not yet written.
TileCal receiver specification - Eric (slides)
We have been informed by Bill Cleland that the LAr receivers will be made at
Pittsburgh; this has now been approved by the US DoE. The only sensible option
for the TileCal receivers is to build them at Pittsburgh too, and to make them
as similar to the LAr ones as possible. They now have people who are willing
to do this, but to get approval (even though we pay) they need a signal-handling
specification to be written. We are supposed to do that. In the absence of analogue
electronics expertise, Eric has volunteered to try to do this, consulting the
Rio group where necessary.
ATLAS week, Stockholm meeting, T/DAQ workshop - Eric
Only two people from our trigger project will be attending the ATLAS overview
week in Clermont-Ferrand. Sam has agreed to give a talk on our status, and has
posted it on the web for comments.
Preparations for the Stockholm meeting on 46 July are going well. One
big decision is to agree on a new milestone schedule (see above).
The TDAQ workshop is the week after Stockholm. Norman will be going. Although
this will concentrate on the DAQ/HLT TDR preparations, there are always useful
things as well as the opportunity to talk to non-TDAQ people at CERN.
Amsterdam and LECC papers - John/Gilles
John has prepared a draft paper for
the Amsterdam conference, and will distribute it for comments. The talk will
have to be combined with calorimeter papers by Arizona (FCAL) and the LAr. Our
preferred choice of speaker is Pascal Perrodo, who has submitted the LAr paper.
There was no other business.
The next UK trigger meeting was tentatively set for Wednesday, 24 July at RAL.
26 June 2002