ATLAS-UK Level-1 Calorimeter Trigger Meeting
Tuesday 16th April 2002 at Birmingham
Click this side Click this side for summaries for slides (pdf) Hardware status VHDL CP chip model at Birmingham.....................Gilles Cluster Processor Module & test cards................Gilles Common Merger Module & DSS I/O Cards....................Ian CP/JEP ROD prototype firmware.........................Bruce Timing Control Module and VME Mount Module.............Adam Stockholm, Mainz and Heidelberg status.................Tony Cabling document status...............................Steve Planning New Firmware..........................................Viraj Schedule...............................................Tony Software status Online software status.............................Murrough The Level-1 Accept Problem!..........................Norman Processor Crate VME Addresses........................Norman General items Draft CPM Paper........................................John Coming meetings Future TDAQ meetings.................................Norman LEB & IEEE.............................................Tony Any other business Next UK meetings
VHDL CP chip model at Birmingham- Gilles (slides)
James provided a model of the CP chip, not the source code, to Birmingham in order to help understanding the functionality of the CP chip. After overcoming several local problems in running the model, the simulation is now working . Previous test vectors generated by Steve have been processed successfully, directly at the input of the chip whereas early simulations were done at the input of the Serialiser. Latency has been found to be of 2 40 MHz ticks for BC demux scheme, 3 ticks for the CP algorithm and an extra 1 to generate RoI information (this is not part of the main processing latency). James' early figures don't agree with these results and he will measure the latency again. The next step will be to process more test vectors. Hit merger and ROC blocks could also be added to the CP block to check that the chain is working correctly.
In discussion, it emerged that the time to simulate the CP chip calibration procedure is 30 minutes (358 microseconds of simulated time). One the hardware, the calibration procedure is needed after every restart - the chip will not work properly if the constants are just loaded.
Cluster Processor Module and test cards - Gilles (slides)
The CPM module has successfully passed its JTAG and Boundary scan tests. Detected assembly faults have been corrected such as re-soldering Quad flat-pack. The BGA packages show no connection errors. Except for VME, connectivity was not checked for blocks connected to outside - connector pins, LVDS de-serialiser and G-link Tx. For the future and at the production stage, an external card could be produced with a dummy FPGA package to test links between the backplane connector and BGAs. The CAN controller was running too hot but the device was not programmed at this stage. The next step will be to bring the CPM to Birmingham and perform checks of the clock, VME access, etc...as enumerated in previous test plans. A crate and backplane will be needed for this test .
Two flash memories hold the complete set of FPGA files, one of them fully dedicated to both configurations of the CP chip. Because the CPM downloads its FPGA devices from Flash memory, it requires the help of an FPGA Configuration Controller. An FPGA could be damaged by downloading a wrong file, and a corrupted file might also be an hazard. To avoid taking any risks with the very expensive FPGA devices on the board, flash configuration memories will be pre-programmed and fitted, and the FPGA configuration will be started from a VME command (i.e not after power up). As extra safety, initially only one FPGA will be configured, such as a Serialiser.
The CPM emulator test card has been made and the second flavour, the CMM emulator, has been assembled. To test the high-speed backplane links between CPMs, an FIO card, looping output pin signal to input, has been thought about. This could be done using a DSS but would require extra work on firmware and software. Another solution is to have a passive board just looping back signals across backplane connectors. Such a board could be made, but would be tricky and not very nice, due to the non-modularity of the backplane from connector to connector and its asymmetry between input and output. To help in debugging the CPM, a crate/module extender board could also be very useful. Looping back signals routes could be also embedded within this. However, various features of the 2mm AMP connector probably make this impractical - not least the insertion force.
Common Merger Module & DSS I/O Cards - Ian (slides)
Five CMM boards have been manufactured and one has been assembled. It has been JTAG tested. A problem has been found with the CPLD JTAG chain which prevents the configuration of the CPLD that controls the configuration of the Crate FPGA. Consequently, the Crate FPGA will not automatically configure when the board is powered up. It can, however, be configured via the FPGA JTAG chain. Automatic configuration will be essential for the final system, so another design iteration of the CMM is required. Testing can proceed with the current module, though, and it is hoped to test as much of this as possible before proceeding to the next design iteration. Currently, the CMM VME interface is being tested, with some success.
CP/JEP ROD prototype firmware - Bruce (slides)
Bruce presented a short update on the status of CP/JEP ROD firmware tests
and software. He reported that the major flow-control problems in the S-Link interface
implementation of the firmware seem to be solved. Updates to the test-system operating
system to RH7.2, foreseen for the slice tests, and work on the module services, moving the
rod test s/w into that framework, have prevented him from returning to detailed systematic
testing of the ROD firmware.
Timing Control Module and VME Mount Module - Adam (slides)
The TCM has been plugged into the crate along with the VMM to verify VME read / write cycles, which has been successful. Memory has been written and read. Standard VME functions such as the CAN reset, one of the tests for the TCM have been tried in the HDMC environment. Have not tested PECL on the backplane to see if it is going to the correct pins. Have not tried further can test provided by Dave Mills.
Further to the last progress report on the VMM, another connector has been removed to enable correct connection to the backplane. A small chunk of PCB (appx 2mm X 80mm) has to be removed from the edge of the board to mount the correct connector. The national instruments MXI module has been plugged into the VMM and then the crate to test for VME read/write cycles successfully. This is the first demonstrated use of the backplane VME-- bus all the way from a processor to a target module.
The layout of the GIO card (a DSS/GTM daughter card) is complete The JTAG chain has been checked by Richard Matson and four cards are on order. The JTAG port has been changed to meet CMC standard, single row connector specification.
Stockholm, Mainz and Heidelberg status - Tony (slides)
Heidelberg status: The PPr ASIC fabrication is finished - 160 dies and 2 wafers. Tests on the first packaged die shows expected behaviour of supply current/temperature with clock frequency. Current is low by ~factor 4, which is probably understood. More dies will be selected for MCM assembly by using needle probe cards.
The first 1 or 2 MCMs will be assembled in Heidelberg by hand in April, when the MCM-adapter test board layout will be complete.
The ReM FPGA design currently overfills the XCV1000E CLBs - work continues.
Mainz status: H/W and S/W upgrades have delayed the JEM0 test programme. The JTAG tests on JEM0 #2 work, the VME firmware is almost complete and the real-time data-path test-bench is being written. HDMC for the JEM is also being prepared.
Stockholm status: The first CPB is in use at RAL, with the second to be shipped to Birmingham soon. Some problems need to be resolved - crate runners length/width, etc. Module warp is evident, causing insertion problems, which will be solved by adding stiffening hardware.
Cabling document status - Steve (slides)
Recent work has consisted of the production of several Excel worksheets and a good deal of conferring by email between Murrough and Steve. The basis of the work comes from Bill Cleland's original LAr receiver cabling document, and the module specifications - largely the information from Appendix A of the PPM specs. The spreadsheets cover the detailed cable numbering and pinouts right from the detectors through to the PPM and beyond through the LVDS cables to the CPM and JEM modules. Various patch panels needed at different stages and detector regions are also specified. A receiver and PPM rack, crate and module layout is also proposed.
The spreadsheets need to be brought together into one document with a suitable general description, which is mostly still to be written. However, it is thought that most of the work is in producing the tables, which has already been done. However, some details need to be confirmed with Bill Cleland and others, and it is felt that the document should go through some sort of review process before being finalised. A draft version at least should be ready before the ASSO deadline. Steve finished by showing examples of the tables that have been produced. There are over 50 tables, some of which carry a great deal of details.
The slides list the RAL ID firmware to be debugged and supported as well as new firmware to be designed.
The Gantt Chart shows the designers working on the existing firmware and the plan for developing new firmware. The work has been prioritised to complete the CP system first and the time scales for this will be June/July 2002 provided the specifications are finalised in time.
When the modules/firmware is in use, any problems should be recorded on a 'problem report' form so all problems and the fixes are recorded formally.
All the QA documentation and the bit files for the firmware is at http://www.te.rl.ac.uk/esdg/atlas-flt/. The QA folder will be password protected.
Schedule and Milestones - Tony (slides)
The October 2001 ASSO list of CP/JEP milestones has been revised to reflect the (unofficial) change to the LHC start-up date. We are now aiming to have the installed and fully-tested calorimeter trigger available by January 2006, which allows an 8-month contingency before the expected September cosmic-ray run.
It is proposed to carry out the JEP sub-system tests in the UK, before moving both CP and JEP sub-systems to Heidelberg for the full Slice Tests. The Gantt chart shows one possible scenario, taking into account the discussion at the Heidelberg joint meeting. This has not yet been discussed with Paul and Uli.
Online software status - Murrough (slides)
Murrough reported on the software status. On the personnel front, Oliver has confirmed he will leave in August. However Mainz will have a new PhD student from June. Meanwhile Steve and Murrough have been distracted by work on the cabling document.
However there has been some progress towards an API for an integrated interface to the database for the module services classes. Steve has also started on CPROD simulation. But the CMM simulation is still needed. Bruce has nearly finished the module services core package and will soon start on the documentation.
There is still a considerable amount of work to do. The main outstanding area remains the organisation of tests and test vectors which was discussed again at the recent software meeting.
The aim is to have enough ready to start testing the software on real CP hardware around June. Then the software can be used to test the hardware. The JEP system is expected to be integrated a bit later, followed by the PP system.
The Level-1 Accept Problem - Norman (slides)
Steve's simulation cannot simulate the ROD readout at present as it doesn't know which data in scrolling memories will be selected for readout by a Level-1 accept. It also doesn't know which 24-bit bunch crossing number will correspond to each L1A. The proposed solution starts with a DSS adaptation to generate the L1A, Orbit, and BGO signals which enter the TTCvi module. Doing this injects a known sequence of L1As at known times. The DSS output will be generated from its internal memory, which will need synchronisation to the 40MHz clock and also to be reset at the same instant as all scrolling memories in the system. We have foreseen a set of TTC commands to do this. Steve had the attractive idea of generating Orbits the same length as the module memories - tests are needed to see if the TTC system can handle this
Processor Crate VME Addresses - Norman (slides)
Now that the VME-- seems to work, we can complete the documentation and confirm the
addressing. The proposal circulated and agreed by email, is that all modules will have and
address allocation of 0.5Mbyte address space in VME--. The bus can handle 32 such
ranges. The first 13 will be empty, followed in sequence by TCM, CMMs, and CPMs/JEMs.
Details are in the VME-- spec document.
John introduced his draft CPM paper, which discusses the CPM design concept and issues relating to I/O, and invited comments on its suitability for IEEE, LECC and Amsterdam. It is important for the trigger to report work in refereed publications.
The discussion agreed that Eric, John, Norman and Tony and would discuss policy for future publications.
The next ATLAS week is at CERN from Monday 22 April to Friday 26 April. Bruce will be going. Following that, the Stockholm collaboration meeting is from 4-6 July. There is an ATLAS TDAQ Workshop at CERN from 8-12 July - a block of rooms are available in the CERN hostel but must be reserved via the ATLAS secretariat by 29th April.
LECC (previously LEB) is on 9-13 September in Colmar. The IEEE is on 10-16 November in Norfolk, Virginia, USA. The IEEE deadline is very close, but we should definitely have submissions to LECC.
There was no other business.
Norman Gee, 23rd April 2002
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